201 lines
5.4 KiB
C
201 lines
5.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Texas Instruments ICSSG Ethernet driver
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*
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* Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
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*
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*/
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#ifndef __NET_TI_ICSSG_CONFIG_H
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#define __NET_TI_ICSSG_CONFIG_H
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struct icssg_buffer_pool_cfg {
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__le32 addr;
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__le32 len;
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} __packed;
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struct icssg_flow_cfg {
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__le16 rx_base_flow;
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__le16 mgm_base_flow;
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} __packed;
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#define PRUETH_PKT_TYPE_CMD 0x10
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#define PRUETH_NAV_PS_DATA_SIZE 16 /* Protocol specific data size */
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#define PRUETH_NAV_SW_DATA_SIZE 16 /* SW related data size */
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#define PRUETH_MAX_TX_DESC 512
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#define PRUETH_MAX_RX_DESC 512
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#define PRUETH_MAX_RX_FLOWS 1 /* excluding default flow */
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#define PRUETH_RX_FLOW_DATA 0
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#define PRUETH_EMAC_BUF_POOL_SIZE SZ_8K
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#define PRUETH_EMAC_POOLS_PER_SLICE 24
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#define PRUETH_EMAC_BUF_POOL_START 8
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#define PRUETH_NUM_BUF_POOLS 8
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#define PRUETH_EMAC_RX_CTX_BUF_SIZE SZ_16K /* per slice */
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#define MSMC_RAM_SIZE \
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(2 * (PRUETH_EMAC_BUF_POOL_SIZE * PRUETH_NUM_BUF_POOLS + \
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PRUETH_EMAC_RX_CTX_BUF_SIZE * 2))
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struct icssg_rxq_ctx {
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__le32 start[3];
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__le32 end;
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} __packed;
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/* Load time Fiwmware Configuration */
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#define ICSSG_FW_MGMT_CMD_HEADER 0x81
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#define ICSSG_FW_MGMT_FDB_CMD_TYPE 0x03
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#define ICSSG_FW_MGMT_CMD_TYPE 0x04
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#define ICSSG_FW_MGMT_PKT 0x80000000
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struct icssg_r30_cmd {
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u32 cmd[4];
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} __packed;
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enum icssg_port_state_cmd {
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ICSSG_EMAC_PORT_DISABLE = 0,
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ICSSG_EMAC_PORT_BLOCK,
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ICSSG_EMAC_PORT_FORWARD,
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ICSSG_EMAC_PORT_FORWARD_WO_LEARNING,
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ICSSG_EMAC_PORT_ACCEPT_ALL,
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ICSSG_EMAC_PORT_ACCEPT_TAGGED,
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ICSSG_EMAC_PORT_ACCEPT_UNTAGGED_N_PRIO,
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ICSSG_EMAC_PORT_TAS_TRIGGER,
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ICSSG_EMAC_PORT_TAS_ENABLE,
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ICSSG_EMAC_PORT_TAS_RESET,
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ICSSG_EMAC_PORT_TAS_DISABLE,
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ICSSG_EMAC_PORT_UC_FLOODING_ENABLE,
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ICSSG_EMAC_PORT_UC_FLOODING_DISABLE,
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ICSSG_EMAC_PORT_MC_FLOODING_ENABLE,
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ICSSG_EMAC_PORT_MC_FLOODING_DISABLE,
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ICSSG_EMAC_PORT_PREMPT_TX_ENABLE,
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ICSSG_EMAC_PORT_PREMPT_TX_DISABLE,
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ICSSG_EMAC_PORT_VLAN_AWARE_ENABLE,
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ICSSG_EMAC_PORT_VLAN_AWARE_DISABLE,
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ICSSG_EMAC_PORT_MAX_COMMANDS
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};
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#define EMAC_NONE 0xffff0000
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#define EMAC_PRU0_P_DI 0xffff0004
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#define EMAC_PRU1_P_DI 0xffff0040
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#define EMAC_TX_P_DI 0xffff0100
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#define EMAC_PRU0_P_EN 0xfffb0000
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#define EMAC_PRU1_P_EN 0xffbf0000
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#define EMAC_TX_P_EN 0xfeff0000
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#define EMAC_P_BLOCK 0xffff0040
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#define EMAC_TX_P_BLOCK 0xffff0200
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#define EMAC_P_UNBLOCK 0xffbf0000
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#define EMAC_TX_P_UNBLOCK 0xfdff0000
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#define EMAC_LEAN_EN 0xfff70000
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#define EMAC_LEAN_DI 0xffff0008
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#define EMAC_ACCEPT_ALL 0xffff0001
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#define EMAC_ACCEPT_TAG 0xfffe0002
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#define EMAC_ACCEPT_PRIOR 0xfffc0000
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/* Config area lies in DRAM */
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#define ICSSG_CONFIG_OFFSET 0x0
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/* Config area lies in shared RAM */
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#define ICSSG_CONFIG_OFFSET_SLICE0 0
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#define ICSSG_CONFIG_OFFSET_SLICE1 0x8000
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#define ICSSG_NUM_NORMAL_PDS 64
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#define ICSSG_NUM_SPECIAL_PDS 16
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#define ICSSG_NORMAL_PD_SIZE 8
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#define ICSSG_SPECIAL_PD_SIZE 20
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#define ICSSG_FLAG_MASK 0xff00ffff
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struct icssg_setclock_desc {
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u8 request;
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u8 restore;
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u8 acknowledgment;
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u8 cmp_status;
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u32 margin;
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u32 cyclecounter0_set;
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u32 cyclecounter1_set;
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u32 iepcount_set;
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u32 rsvd1;
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u32 rsvd2;
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u32 CMP0_current;
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u32 iepcount_current;
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u32 difference;
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u32 cyclecounter0_new;
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u32 cyclecounter1_new;
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u32 CMP0_new;
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} __packed;
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#define ICSSG_CMD_POP_SLICE0 56
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#define ICSSG_CMD_POP_SLICE1 60
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#define ICSSG_CMD_PUSH_SLICE0 57
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#define ICSSG_CMD_PUSH_SLICE1 61
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#define ICSSG_RSP_POP_SLICE0 58
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#define ICSSG_RSP_POP_SLICE1 62
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#define ICSSG_RSP_PUSH_SLICE0 56
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#define ICSSG_RSP_PUSH_SLICE1 60
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#define ICSSG_TS_POP_SLICE0 59
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#define ICSSG_TS_POP_SLICE1 63
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#define ICSSG_TS_PUSH_SLICE0 40
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#define ICSSG_TS_PUSH_SLICE1 41
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/* FDB FID_C2 flag definitions */
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/* Indicates host port membership.*/
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#define ICSSG_FDB_ENTRY_P0_MEMBERSHIP BIT(0)
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/* Indicates that MAC ID is connected to physical port 1 */
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#define ICSSG_FDB_ENTRY_P1_MEMBERSHIP BIT(1)
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/* Indicates that MAC ID is connected to physical port 2 */
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#define ICSSG_FDB_ENTRY_P2_MEMBERSHIP BIT(2)
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/* Ageable bit is set for learned entries and cleared for static entries */
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#define ICSSG_FDB_ENTRY_AGEABLE BIT(3)
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/* If set for DA then packet is determined to be a special packet */
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#define ICSSG_FDB_ENTRY_BLOCK BIT(4)
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/* If set for DA then the SA from the packet is not learned */
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#define ICSSG_FDB_ENTRY_SECURE BIT(5)
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/* If set, it means packet has been seen recently with source address + FID
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* matching MAC address/FID of entry
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*/
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#define ICSSG_FDB_ENTRY_TOUCHED BIT(6)
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/* Set if entry is valid */
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#define ICSSG_FDB_ENTRY_VALID BIT(7)
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/**
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* struct prueth_vlan_tbl - VLAN table entries struct in ICSSG SMEM
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* @fid_c1: membership and forwarding rules flag to this table. See
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* above to defines for bit definitions
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* @fid: FDB index for this VID (there is 1-1 mapping b/w VID and FID)
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*/
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struct prueth_vlan_tbl {
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u8 fid_c1;
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u8 fid;
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} __packed;
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/**
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* struct prueth_fdb_slot - Result of FDB slot lookup
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* @mac: MAC address
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* @fid: fid to be associated with MAC
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* @fid_c2: FID_C2 entry for this MAC
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*/
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struct prueth_fdb_slot {
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u8 mac[ETH_ALEN];
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u8 fid;
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u8 fid_c2;
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} __packed;
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enum icssg_ietfpe_verify_states {
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ICSSG_IETFPE_STATE_UNKNOWN = 0,
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ICSSG_IETFPE_STATE_INITIAL,
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ICSSG_IETFPE_STATE_VERIFYING,
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ICSSG_IETFPE_STATE_SUCCEEDED,
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ICSSG_IETFPE_STATE_FAILED,
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ICSSG_IETFPE_STATE_DISABLED
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};
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#endif /* __NET_TI_ICSSG_CONFIG_H */
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