472 lines
13 KiB
C
472 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/* ICSSG Ethernet driver
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*
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* Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com
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*/
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#include <linux/iopoll.h>
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#include <linux/regmap.h>
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#include <uapi/linux/if_ether.h>
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#include "icssg_config.h"
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#include "icssg_prueth.h"
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#include "icssg_switch_map.h"
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#include "icssg_mii_rt.h"
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/* TX IPG Values to be set for 100M link speed. These values are
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* in ocp_clk cycles. So need change if ocp_clk is changed for a specific
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* h/w design.
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*/
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/* IPG is in core_clk cycles */
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#define MII_RT_TX_IPG_100M 0x17
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#define MII_RT_TX_IPG_1G 0xb
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#define ICSSG_QUEUES_MAX 64
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#define ICSSG_QUEUE_OFFSET 0xd00
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#define ICSSG_QUEUE_PEEK_OFFSET 0xe00
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#define ICSSG_QUEUE_CNT_OFFSET 0xe40
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#define ICSSG_QUEUE_RESET_OFFSET 0xf40
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#define ICSSG_NUM_TX_QUEUES 8
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#define RECYCLE_Q_SLICE0 16
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#define RECYCLE_Q_SLICE1 17
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#define ICSSG_NUM_OTHER_QUEUES 5 /* port, host and special queues */
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#define PORT_HI_Q_SLICE0 32
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#define PORT_LO_Q_SLICE0 33
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#define HOST_HI_Q_SLICE0 34
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#define HOST_LO_Q_SLICE0 35
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#define HOST_SPL_Q_SLICE0 40 /* Special Queue */
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#define PORT_HI_Q_SLICE1 36
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#define PORT_LO_Q_SLICE1 37
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#define HOST_HI_Q_SLICE1 38
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#define HOST_LO_Q_SLICE1 39
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#define HOST_SPL_Q_SLICE1 41 /* Special Queue */
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#define MII_RXCFG_DEFAULT (PRUSS_MII_RT_RXCFG_RX_ENABLE | \
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PRUSS_MII_RT_RXCFG_RX_DATA_RDY_MODE_DIS | \
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PRUSS_MII_RT_RXCFG_RX_L2_EN | \
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PRUSS_MII_RT_RXCFG_RX_L2_EOF_SCLR_DIS)
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#define MII_TXCFG_DEFAULT (PRUSS_MII_RT_TXCFG_TX_ENABLE | \
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PRUSS_MII_RT_TXCFG_TX_AUTO_PREAMBLE | \
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PRUSS_MII_RT_TXCFG_TX_32_MODE_EN | \
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PRUSS_MII_RT_TXCFG_TX_IPG_WIRE_CLK_EN)
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#define ICSSG_CFG_DEFAULT (ICSSG_CFG_TX_L1_EN | \
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ICSSG_CFG_TX_L2_EN | ICSSG_CFG_RX_L2_G_EN | \
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ICSSG_CFG_TX_PRU_EN | \
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ICSSG_CFG_SGMII_MODE)
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#define FDB_GEN_CFG1 0x60
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#define SMEM_VLAN_OFFSET 8
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#define SMEM_VLAN_OFFSET_MASK GENMASK(25, 8)
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#define FDB_GEN_CFG2 0x64
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#define FDB_VLAN_EN BIT(6)
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#define FDB_HOST_EN BIT(2)
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#define FDB_PRU1_EN BIT(1)
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#define FDB_PRU0_EN BIT(0)
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#define FDB_EN_ALL (FDB_PRU0_EN | FDB_PRU1_EN | \
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FDB_HOST_EN | FDB_VLAN_EN)
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/**
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* struct map - ICSSG Queue Map
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* @queue: Queue number
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* @pd_addr_start: Packet descriptor queue reserved memory
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* @flags: Flags
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* @special: Indicates whether this queue is a special queue or not
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*/
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struct map {
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int queue;
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u32 pd_addr_start;
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u32 flags;
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bool special;
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};
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/* Hardware queue map for ICSSG */
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static const struct map hwq_map[2][ICSSG_NUM_OTHER_QUEUES] = {
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{
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{ PORT_HI_Q_SLICE0, PORT_DESC0_HI, 0x200000, 0 },
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{ PORT_LO_Q_SLICE0, PORT_DESC0_LO, 0, 0 },
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{ HOST_HI_Q_SLICE0, HOST_DESC0_HI, 0x200000, 0 },
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{ HOST_LO_Q_SLICE0, HOST_DESC0_LO, 0, 0 },
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{ HOST_SPL_Q_SLICE0, HOST_SPPD0, 0x400000, 1 },
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},
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{
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{ PORT_HI_Q_SLICE1, PORT_DESC1_HI, 0xa00000, 0 },
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{ PORT_LO_Q_SLICE1, PORT_DESC1_LO, 0x800000, 0 },
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{ HOST_HI_Q_SLICE1, HOST_DESC1_HI, 0xa00000, 0 },
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{ HOST_LO_Q_SLICE1, HOST_DESC1_LO, 0x800000, 0 },
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{ HOST_SPL_Q_SLICE1, HOST_SPPD1, 0xc00000, 1 },
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},
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};
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static void icssg_config_mii_init(struct prueth_emac *emac)
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{
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u32 rxcfg, txcfg, rxcfg_reg, txcfg_reg, pcnt_reg;
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struct prueth *prueth = emac->prueth;
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int slice = prueth_emac_slice(emac);
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struct regmap *mii_rt;
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mii_rt = prueth->mii_rt;
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rxcfg_reg = (slice == ICSS_MII0) ? PRUSS_MII_RT_RXCFG0 :
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PRUSS_MII_RT_RXCFG1;
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txcfg_reg = (slice == ICSS_MII0) ? PRUSS_MII_RT_TXCFG0 :
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PRUSS_MII_RT_TXCFG1;
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pcnt_reg = (slice == ICSS_MII0) ? PRUSS_MII_RT_RX_PCNT0 :
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PRUSS_MII_RT_RX_PCNT1;
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rxcfg = MII_RXCFG_DEFAULT;
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txcfg = MII_TXCFG_DEFAULT;
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if (slice == ICSS_MII1)
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rxcfg |= PRUSS_MII_RT_RXCFG_RX_MUX_SEL;
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/* In MII mode TX lines swapped inside ICSSG, so TX_MUX_SEL cfg need
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* to be swapped also comparing to RGMII mode.
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*/
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if (emac->phy_if == PHY_INTERFACE_MODE_MII && slice == ICSS_MII0)
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txcfg |= PRUSS_MII_RT_TXCFG_TX_MUX_SEL;
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else if (emac->phy_if != PHY_INTERFACE_MODE_MII && slice == ICSS_MII1)
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txcfg |= PRUSS_MII_RT_TXCFG_TX_MUX_SEL;
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regmap_write(mii_rt, rxcfg_reg, rxcfg);
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regmap_write(mii_rt, txcfg_reg, txcfg);
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regmap_write(mii_rt, pcnt_reg, 0x1);
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}
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static void icssg_miig_queues_init(struct prueth *prueth, int slice)
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{
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struct regmap *miig_rt = prueth->miig_rt;
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void __iomem *smem = prueth->shram.va;
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u8 pd[ICSSG_SPECIAL_PD_SIZE];
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int queue = 0, i, j;
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u32 *pdword;
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/* reset hwqueues */
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if (slice)
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queue = ICSSG_NUM_TX_QUEUES;
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for (i = 0; i < ICSSG_NUM_TX_QUEUES; i++) {
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regmap_write(miig_rt, ICSSG_QUEUE_RESET_OFFSET, queue);
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queue++;
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}
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queue = slice ? RECYCLE_Q_SLICE1 : RECYCLE_Q_SLICE0;
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regmap_write(miig_rt, ICSSG_QUEUE_RESET_OFFSET, queue);
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for (i = 0; i < ICSSG_NUM_OTHER_QUEUES; i++) {
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regmap_write(miig_rt, ICSSG_QUEUE_RESET_OFFSET,
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hwq_map[slice][i].queue);
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}
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/* initialize packet descriptors in SMEM */
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/* push pakcet descriptors to hwqueues */
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pdword = (u32 *)pd;
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for (j = 0; j < ICSSG_NUM_OTHER_QUEUES; j++) {
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const struct map *mp;
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int pd_size, num_pds;
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u32 pdaddr;
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mp = &hwq_map[slice][j];
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if (mp->special) {
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pd_size = ICSSG_SPECIAL_PD_SIZE;
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num_pds = ICSSG_NUM_SPECIAL_PDS;
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} else {
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pd_size = ICSSG_NORMAL_PD_SIZE;
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num_pds = ICSSG_NUM_NORMAL_PDS;
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}
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for (i = 0; i < num_pds; i++) {
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memset(pd, 0, pd_size);
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pdword[0] &= ICSSG_FLAG_MASK;
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pdword[0] |= mp->flags;
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pdaddr = mp->pd_addr_start + i * pd_size;
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memcpy_toio(smem + pdaddr, pd, pd_size);
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queue = mp->queue;
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regmap_write(miig_rt, ICSSG_QUEUE_OFFSET + 4 * queue,
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pdaddr);
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}
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}
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}
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void icssg_config_ipg(struct prueth_emac *emac)
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{
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struct prueth *prueth = emac->prueth;
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int slice = prueth_emac_slice(emac);
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switch (emac->speed) {
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case SPEED_1000:
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icssg_mii_update_ipg(prueth->mii_rt, slice, MII_RT_TX_IPG_1G);
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break;
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case SPEED_100:
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icssg_mii_update_ipg(prueth->mii_rt, slice, MII_RT_TX_IPG_100M);
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break;
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case SPEED_10:
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/* IPG for 10M is same as 100M */
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icssg_mii_update_ipg(prueth->mii_rt, slice, MII_RT_TX_IPG_100M);
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break;
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default:
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/* Other links speeds not supported */
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netdev_err(emac->ndev, "Unsupported link speed\n");
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return;
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}
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}
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static void emac_r30_cmd_init(struct prueth_emac *emac)
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{
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struct icssg_r30_cmd __iomem *p;
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int i;
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p = emac->dram.va + MGR_R30_CMD_OFFSET;
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for (i = 0; i < 4; i++)
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writel(EMAC_NONE, &p->cmd[i]);
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}
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static int emac_r30_is_done(struct prueth_emac *emac)
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{
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const struct icssg_r30_cmd __iomem *p;
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u32 cmd;
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int i;
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p = emac->dram.va + MGR_R30_CMD_OFFSET;
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for (i = 0; i < 4; i++) {
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cmd = readl(&p->cmd[i]);
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if (cmd != EMAC_NONE)
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return 0;
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}
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return 1;
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}
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static int prueth_emac_buffer_setup(struct prueth_emac *emac)
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{
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struct icssg_buffer_pool_cfg __iomem *bpool_cfg;
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struct icssg_rxq_ctx __iomem *rxq_ctx;
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struct prueth *prueth = emac->prueth;
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int slice = prueth_emac_slice(emac);
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u32 addr;
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int i;
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/* Layout to have 64KB aligned buffer pool
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* |BPOOL0|BPOOL1|RX_CTX0|RX_CTX1|
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*/
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addr = lower_32_bits(prueth->msmcram.pa);
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if (slice)
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addr += PRUETH_NUM_BUF_POOLS * PRUETH_EMAC_BUF_POOL_SIZE;
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if (addr % SZ_64K) {
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dev_warn(prueth->dev, "buffer pool needs to be 64KB aligned\n");
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return -EINVAL;
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}
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bpool_cfg = emac->dram.va + BUFFER_POOL_0_ADDR_OFFSET;
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/* workaround for f/w bug. bpool 0 needs to be initilalized */
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writel(addr, &bpool_cfg[0].addr);
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writel(0, &bpool_cfg[0].len);
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for (i = PRUETH_EMAC_BUF_POOL_START;
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i < PRUETH_EMAC_BUF_POOL_START + PRUETH_NUM_BUF_POOLS;
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i++) {
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writel(addr, &bpool_cfg[i].addr);
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writel(PRUETH_EMAC_BUF_POOL_SIZE, &bpool_cfg[i].len);
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addr += PRUETH_EMAC_BUF_POOL_SIZE;
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}
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if (!slice)
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addr += PRUETH_NUM_BUF_POOLS * PRUETH_EMAC_BUF_POOL_SIZE;
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else
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addr += PRUETH_EMAC_RX_CTX_BUF_SIZE * 2;
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/* Pre-emptible RX buffer queue */
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rxq_ctx = emac->dram.va + HOST_RX_Q_PRE_CONTEXT_OFFSET;
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for (i = 0; i < 3; i++)
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writel(addr, &rxq_ctx->start[i]);
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addr += PRUETH_EMAC_RX_CTX_BUF_SIZE;
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writel(addr, &rxq_ctx->end);
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/* Express RX buffer queue */
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rxq_ctx = emac->dram.va + HOST_RX_Q_EXP_CONTEXT_OFFSET;
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for (i = 0; i < 3; i++)
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writel(addr, &rxq_ctx->start[i]);
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addr += PRUETH_EMAC_RX_CTX_BUF_SIZE;
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writel(addr, &rxq_ctx->end);
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return 0;
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}
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static void icssg_init_emac_mode(struct prueth *prueth)
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{
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/* When the device is configured as a bridge and it is being brought
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* back to the emac mode, the host mac address has to be set as 0.
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*/
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u8 mac[ETH_ALEN] = { 0 };
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if (prueth->emacs_initialized)
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return;
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regmap_update_bits(prueth->miig_rt, FDB_GEN_CFG1,
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SMEM_VLAN_OFFSET_MASK, 0);
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regmap_write(prueth->miig_rt, FDB_GEN_CFG2, 0);
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/* Clear host MAC address */
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icssg_class_set_host_mac_addr(prueth->miig_rt, mac);
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}
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int icssg_config(struct prueth *prueth, struct prueth_emac *emac, int slice)
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{
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void __iomem *config = emac->dram.va + ICSSG_CONFIG_OFFSET;
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struct icssg_flow_cfg __iomem *flow_cfg;
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int ret;
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icssg_init_emac_mode(prueth);
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memset_io(config, 0, TAS_GATE_MASK_LIST0);
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icssg_miig_queues_init(prueth, slice);
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emac->speed = SPEED_1000;
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emac->duplex = DUPLEX_FULL;
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if (!phy_interface_mode_is_rgmii(emac->phy_if)) {
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emac->speed = SPEED_100;
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emac->duplex = DUPLEX_FULL;
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}
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regmap_update_bits(prueth->miig_rt, ICSSG_CFG_OFFSET,
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ICSSG_CFG_DEFAULT, ICSSG_CFG_DEFAULT);
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icssg_miig_set_interface_mode(prueth->miig_rt, slice, emac->phy_if);
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icssg_config_mii_init(emac);
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icssg_config_ipg(emac);
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icssg_update_rgmii_cfg(prueth->miig_rt, emac);
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/* set GPI mode */
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pruss_cfg_gpimode(prueth->pruss, prueth->pru_id[slice],
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PRUSS_GPI_MODE_MII);
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/* enable XFR shift for PRU and RTU */
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pruss_cfg_xfr_enable(prueth->pruss, PRU_TYPE_PRU, true);
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pruss_cfg_xfr_enable(prueth->pruss, PRU_TYPE_RTU, true);
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/* set C28 to 0x100 */
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pru_rproc_set_ctable(prueth->pru[slice], PRU_C28, 0x100 << 8);
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pru_rproc_set_ctable(prueth->rtu[slice], PRU_C28, 0x100 << 8);
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pru_rproc_set_ctable(prueth->txpru[slice], PRU_C28, 0x100 << 8);
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flow_cfg = config + PSI_L_REGULAR_FLOW_ID_BASE_OFFSET;
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writew(emac->rx_flow_id_base, &flow_cfg->rx_base_flow);
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writew(0, &flow_cfg->mgm_base_flow);
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writeb(0, config + SPL_PKT_DEFAULT_PRIORITY);
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writeb(0, config + QUEUE_NUM_UNTAGGED);
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ret = prueth_emac_buffer_setup(emac);
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if (ret)
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return ret;
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emac_r30_cmd_init(emac);
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return 0;
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}
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/* Bitmask for ICSSG r30 commands */
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static const struct icssg_r30_cmd emac_r32_bitmask[] = {
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{{0xffff0004, 0xffff0100, 0xffff0004, EMAC_NONE}}, /* EMAC_PORT_DISABLE */
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{{0xfffb0040, 0xfeff0200, 0xfeff0200, EMAC_NONE}}, /* EMAC_PORT_BLOCK */
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{{0xffbb0000, 0xfcff0000, 0xdcfb0000, EMAC_NONE}}, /* EMAC_PORT_FORWARD */
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{{0xffbb0000, 0xfcff0000, 0xfcff2000, EMAC_NONE}}, /* EMAC_PORT_FORWARD_WO_LEARNING */
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{{0xffff0001, EMAC_NONE, EMAC_NONE, EMAC_NONE}}, /* ACCEPT ALL */
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{{0xfffe0002, EMAC_NONE, EMAC_NONE, EMAC_NONE}}, /* ACCEPT TAGGED */
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{{0xfffc0000, EMAC_NONE, EMAC_NONE, EMAC_NONE}}, /* ACCEPT UNTAGGED and PRIO */
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{{EMAC_NONE, 0xffff0020, EMAC_NONE, EMAC_NONE}}, /* TAS Trigger List change */
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{{EMAC_NONE, 0xdfff1000, EMAC_NONE, EMAC_NONE}}, /* TAS set state ENABLE*/
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{{EMAC_NONE, 0xefff2000, EMAC_NONE, EMAC_NONE}}, /* TAS set state RESET*/
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{{EMAC_NONE, 0xcfff0000, EMAC_NONE, EMAC_NONE}}, /* TAS set state DISABLE*/
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{{EMAC_NONE, EMAC_NONE, 0xffff0400, EMAC_NONE}}, /* UC flooding ENABLE*/
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{{EMAC_NONE, EMAC_NONE, 0xfbff0000, EMAC_NONE}}, /* UC flooding DISABLE*/
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{{EMAC_NONE, EMAC_NONE, 0xffff0800, EMAC_NONE}}, /* MC flooding ENABLE*/
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{{EMAC_NONE, EMAC_NONE, 0xf7ff0000, EMAC_NONE}}, /* MC flooding DISABLE*/
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{{EMAC_NONE, 0xffff4000, EMAC_NONE, EMAC_NONE}}, /* Preemption on Tx ENABLE*/
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{{EMAC_NONE, 0xbfff0000, EMAC_NONE, EMAC_NONE}}, /* Preemption on Tx DISABLE*/
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{{0xffff0010, EMAC_NONE, 0xffff0010, EMAC_NONE}}, /* VLAN AWARE*/
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{{0xffef0000, EMAC_NONE, 0xffef0000, EMAC_NONE}} /* VLAN UNWARE*/
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};
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int emac_set_port_state(struct prueth_emac *emac,
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enum icssg_port_state_cmd cmd)
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{
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struct icssg_r30_cmd __iomem *p;
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int ret = -ETIMEDOUT;
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int done = 0;
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int i;
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p = emac->dram.va + MGR_R30_CMD_OFFSET;
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if (cmd >= ICSSG_EMAC_PORT_MAX_COMMANDS) {
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netdev_err(emac->ndev, "invalid port command\n");
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return -EINVAL;
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}
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/* only one command at a time allowed to firmware */
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mutex_lock(&emac->cmd_lock);
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for (i = 0; i < 4; i++)
|
|
writel(emac_r32_bitmask[cmd].cmd[i], &p->cmd[i]);
|
|
|
|
/* wait for done */
|
|
ret = read_poll_timeout(emac_r30_is_done, done, done == 1,
|
|
1000, 10000, false, emac);
|
|
|
|
if (ret == -ETIMEDOUT)
|
|
netdev_err(emac->ndev, "timeout waiting for command done\n");
|
|
|
|
mutex_unlock(&emac->cmd_lock);
|
|
|
|
return ret;
|
|
}
|
|
|
|
void icssg_config_half_duplex(struct prueth_emac *emac)
|
|
{
|
|
u32 val;
|
|
|
|
if (!emac->half_duplex)
|
|
return;
|
|
|
|
val = get_random_u32();
|
|
writel(val, emac->dram.va + HD_RAND_SEED_OFFSET);
|
|
}
|
|
|
|
void icssg_config_set_speed(struct prueth_emac *emac)
|
|
{
|
|
u8 fw_speed;
|
|
|
|
switch (emac->speed) {
|
|
case SPEED_1000:
|
|
fw_speed = FW_LINK_SPEED_1G;
|
|
break;
|
|
case SPEED_100:
|
|
fw_speed = FW_LINK_SPEED_100M;
|
|
break;
|
|
case SPEED_10:
|
|
fw_speed = FW_LINK_SPEED_10M;
|
|
break;
|
|
default:
|
|
/* Other links speeds not supported */
|
|
netdev_err(emac->ndev, "Unsupported link speed\n");
|
|
return;
|
|
}
|
|
|
|
if (emac->duplex == DUPLEX_HALF)
|
|
fw_speed |= FW_LINK_SPEED_HD;
|
|
|
|
writeb(fw_speed, emac->dram.va + PORT_LINK_SPEED_OFFSET);
|
|
}
|