581 lines
16 KiB
C
581 lines
16 KiB
C
// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2022 Intel Corporation
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*/
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#include "xe_mocs.h"
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#include "regs/xe_gt_regs.h"
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#include "xe_bo.h"
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#include "xe_device.h"
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#include "xe_exec_queue.h"
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#include "xe_gt.h"
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#include "xe_gt_mcr.h"
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#include "xe_mmio.h"
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#include "xe_platform_types.h"
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#include "xe_step_types.h"
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#if IS_ENABLED(CONFIG_DRM_XE_DEBUG)
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#define mocs_dbg drm_dbg
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#else
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__printf(2, 3)
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static inline void mocs_dbg(const struct drm_device *dev,
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const char *format, ...)
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{ /* noop */ }
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#endif
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enum {
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HAS_GLOBAL_MOCS = BIT(0),
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HAS_LNCF_MOCS = BIT(1),
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};
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struct xe_mocs_entry {
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u32 control_value;
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u16 l3cc_value;
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u16 used;
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};
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struct xe_mocs_info {
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unsigned int size;
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unsigned int n_entries;
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const struct xe_mocs_entry *table;
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u8 uc_index;
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u8 wb_index;
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u8 unused_entries_index;
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};
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/* Defines for the tables (XXX_MOCS_0 - XXX_MOCS_63) */
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#define _LE_CACHEABILITY(value) ((value) << 0)
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#define _LE_TGT_CACHE(value) ((value) << 2)
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#define LE_LRUM(value) ((value) << 4)
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#define LE_AOM(value) ((value) << 6)
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#define LE_RSC(value) ((value) << 7)
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#define LE_SCC(value) ((value) << 8)
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#define LE_PFM(value) ((value) << 11)
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#define LE_SCF(value) ((value) << 14)
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#define LE_COS(value) ((value) << 15)
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#define LE_SSE(value) ((value) << 17)
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/* Defines for the tables (LNCFMOCS0 - LNCFMOCS31) - two entries per word */
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#define L3_ESC(value) ((value) << 0)
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#define L3_SCC(value) ((value) << 1)
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#define _L3_CACHEABILITY(value) ((value) << 4)
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#define L3_GLBGO(value) ((value) << 6)
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#define L3_LKUP(value) ((value) << 7)
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/* Defines for the tables (GLOB_MOCS_0 - GLOB_MOCS_16) */
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#define IG_PAT REG_BIT(8)
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#define L3_CACHE_POLICY_MASK REG_GENMASK(5, 4)
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#define L4_CACHE_POLICY_MASK REG_GENMASK(3, 2)
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/* Helper defines */
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#define XELP_NUM_MOCS_ENTRIES 64 /* 63-64 are reserved, but configured. */
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#define PVC_NUM_MOCS_ENTRIES 3
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#define MTL_NUM_MOCS_ENTRIES 16
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#define XE2_NUM_MOCS_ENTRIES 16
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/* (e)LLC caching options */
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/*
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* Note: LE_0_PAGETABLE works only up to Gen11; for newer gens it means
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* the same as LE_UC
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*/
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#define LE_0_PAGETABLE _LE_CACHEABILITY(0)
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#define LE_1_UC _LE_CACHEABILITY(1)
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#define LE_2_WT _LE_CACHEABILITY(2)
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#define LE_3_WB _LE_CACHEABILITY(3)
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/* Target cache */
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#define LE_TC_0_PAGETABLE _LE_TGT_CACHE(0)
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#define LE_TC_1_LLC _LE_TGT_CACHE(1)
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#define LE_TC_2_LLC_ELLC _LE_TGT_CACHE(2)
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#define LE_TC_3_LLC_ELLC_ALT _LE_TGT_CACHE(3)
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/* L3 caching options */
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#define L3_0_DIRECT _L3_CACHEABILITY(0)
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#define L3_1_UC _L3_CACHEABILITY(1)
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#define L3_2_RESERVED _L3_CACHEABILITY(2)
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#define L3_3_WB _L3_CACHEABILITY(3)
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/* L4 caching options */
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#define L4_0_WB REG_FIELD_PREP(L4_CACHE_POLICY_MASK, 0)
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#define L4_1_WT REG_FIELD_PREP(L4_CACHE_POLICY_MASK, 1)
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#define L4_3_UC REG_FIELD_PREP(L4_CACHE_POLICY_MASK, 3)
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#define XE2_L3_0_WB REG_FIELD_PREP(L3_CACHE_POLICY_MASK, 0)
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/* XD: WB Transient Display */
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#define XE2_L3_1_XD REG_FIELD_PREP(L3_CACHE_POLICY_MASK, 1)
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#define XE2_L3_3_UC REG_FIELD_PREP(L3_CACHE_POLICY_MASK, 3)
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#define MOCS_ENTRY(__idx, __control_value, __l3cc_value) \
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[__idx] = { \
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.control_value = __control_value, \
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.l3cc_value = __l3cc_value, \
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.used = 1, \
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}
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/*
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* MOCS tables
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*
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* These are the MOCS tables that are programmed across all the rings.
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* The control value is programmed to all the rings that support the
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* MOCS registers. While the l3cc_values are only programmed to the
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* LNCFCMOCS0 - LNCFCMOCS32 registers.
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*
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* These tables are intended to be kept reasonably consistent across
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* HW platforms, and for ICL+, be identical across OSes. To achieve
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* that, the list of entries is published as part of bspec.
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*
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* Entries not part of the following tables are undefined as far as userspace is
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* concerned and shouldn't be relied upon. The last few entries are reserved by
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* the hardware. They should be initialized according to bspec and never used.
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*
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* NOTE1: These tables are part of bspec and defined as part of the hardware
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* interface. It is expected that, for specific hardware platform, existing
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* entries will remain constant and the table will only be updated by adding new
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* entries, filling unused positions.
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*
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* NOTE2: Reserved and unspecified MOCS indices have been set to L3 WB. These
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* reserved entries should never be used. They may be changed to low performant
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* variants with better coherency in the future if more entries are needed.
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*/
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static const struct xe_mocs_entry gen12_mocs_desc[] = {
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/* Base - L3 + LLC */
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MOCS_ENTRY(2,
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LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
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L3_3_WB),
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/* Base - Uncached */
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MOCS_ENTRY(3,
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LE_1_UC | LE_TC_1_LLC,
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L3_1_UC),
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/* Base - L3 */
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MOCS_ENTRY(4,
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LE_1_UC | LE_TC_1_LLC,
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L3_3_WB),
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/* Base - LLC */
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MOCS_ENTRY(5,
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LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
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L3_1_UC),
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/* Age 0 - LLC */
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MOCS_ENTRY(6,
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LE_3_WB | LE_TC_1_LLC | LE_LRUM(1),
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L3_1_UC),
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/* Age 0 - L3 + LLC */
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MOCS_ENTRY(7,
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LE_3_WB | LE_TC_1_LLC | LE_LRUM(1),
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L3_3_WB),
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/* Age: Don't Chg. - LLC */
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MOCS_ENTRY(8,
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LE_3_WB | LE_TC_1_LLC | LE_LRUM(2),
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L3_1_UC),
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/* Age: Don't Chg. - L3 + LLC */
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MOCS_ENTRY(9,
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LE_3_WB | LE_TC_1_LLC | LE_LRUM(2),
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L3_3_WB),
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/* No AOM - LLC */
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MOCS_ENTRY(10,
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LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_AOM(1),
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L3_1_UC),
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/* No AOM - L3 + LLC */
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MOCS_ENTRY(11,
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LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_AOM(1),
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L3_3_WB),
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/* No AOM; Age 0 - LLC */
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MOCS_ENTRY(12,
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LE_3_WB | LE_TC_1_LLC | LE_LRUM(1) | LE_AOM(1),
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L3_1_UC),
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/* No AOM; Age 0 - L3 + LLC */
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MOCS_ENTRY(13,
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LE_3_WB | LE_TC_1_LLC | LE_LRUM(1) | LE_AOM(1),
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L3_3_WB),
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/* No AOM; Age:DC - LLC */
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MOCS_ENTRY(14,
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LE_3_WB | LE_TC_1_LLC | LE_LRUM(2) | LE_AOM(1),
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L3_1_UC),
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/* No AOM; Age:DC - L3 + LLC */
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MOCS_ENTRY(15,
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LE_3_WB | LE_TC_1_LLC | LE_LRUM(2) | LE_AOM(1),
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L3_3_WB),
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/* Self-Snoop - L3 + LLC */
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MOCS_ENTRY(18,
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LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_SSE(3),
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L3_3_WB),
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/* Skip Caching - L3 + LLC(12.5%) */
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MOCS_ENTRY(19,
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LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_SCC(7),
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L3_3_WB),
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/* Skip Caching - L3 + LLC(25%) */
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MOCS_ENTRY(20,
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LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_SCC(3),
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L3_3_WB),
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/* Skip Caching - L3 + LLC(50%) */
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MOCS_ENTRY(21,
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LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_SCC(1),
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L3_3_WB),
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/* Skip Caching - L3 + LLC(75%) */
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MOCS_ENTRY(22,
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LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_RSC(1) | LE_SCC(3),
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L3_3_WB),
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/* Skip Caching - L3 + LLC(87.5%) */
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MOCS_ENTRY(23,
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LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_RSC(1) | LE_SCC(7),
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L3_3_WB),
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/* Implicitly enable L1 - HDC:L1 + L3 + LLC */
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MOCS_ENTRY(48,
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LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
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L3_3_WB),
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/* Implicitly enable L1 - HDC:L1 + L3 */
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MOCS_ENTRY(49,
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LE_1_UC | LE_TC_1_LLC,
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L3_3_WB),
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/* Implicitly enable L1 - HDC:L1 + LLC */
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MOCS_ENTRY(50,
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LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
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L3_1_UC),
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/* Implicitly enable L1 - HDC:L1 */
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MOCS_ENTRY(51,
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LE_1_UC | LE_TC_1_LLC,
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L3_1_UC),
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/* HW Special Case (CCS) */
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MOCS_ENTRY(60,
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LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
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L3_1_UC),
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/* HW Special Case (Displayable) */
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MOCS_ENTRY(61,
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LE_1_UC | LE_TC_1_LLC,
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L3_3_WB),
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/* HW Reserved - SW program but never use */
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MOCS_ENTRY(62,
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LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
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L3_1_UC),
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/* HW Reserved - SW program but never use */
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MOCS_ENTRY(63,
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LE_3_WB | LE_TC_1_LLC | LE_LRUM(3),
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L3_1_UC)
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};
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static const struct xe_mocs_entry dg1_mocs_desc[] = {
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/* UC */
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MOCS_ENTRY(1, 0, L3_1_UC),
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/* WB - L3 */
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MOCS_ENTRY(5, 0, L3_3_WB),
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/* WB - L3 50% */
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MOCS_ENTRY(6, 0, L3_ESC(1) | L3_SCC(1) | L3_3_WB),
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/* WB - L3 25% */
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MOCS_ENTRY(7, 0, L3_ESC(1) | L3_SCC(3) | L3_3_WB),
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/* WB - L3 12.5% */
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MOCS_ENTRY(8, 0, L3_ESC(1) | L3_SCC(7) | L3_3_WB),
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/* HDC:L1 + L3 */
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MOCS_ENTRY(48, 0, L3_3_WB),
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/* HDC:L1 */
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MOCS_ENTRY(49, 0, L3_1_UC),
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/* HW Reserved */
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MOCS_ENTRY(60, 0, L3_1_UC),
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MOCS_ENTRY(61, 0, L3_1_UC),
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MOCS_ENTRY(62, 0, L3_1_UC),
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MOCS_ENTRY(63, 0, L3_1_UC),
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};
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static const struct xe_mocs_entry dg2_mocs_desc[] = {
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/* UC - Coherent; GO:L3 */
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MOCS_ENTRY(0, 0, L3_1_UC | L3_LKUP(1)),
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/* UC - Coherent; GO:Memory */
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MOCS_ENTRY(1, 0, L3_1_UC | L3_GLBGO(1) | L3_LKUP(1)),
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/* UC - Non-Coherent; GO:Memory */
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MOCS_ENTRY(2, 0, L3_1_UC | L3_GLBGO(1)),
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/* WB - LC */
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MOCS_ENTRY(3, 0, L3_3_WB | L3_LKUP(1)),
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};
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static const struct xe_mocs_entry dg2_mocs_desc_g10_ax[] = {
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/* Wa_14011441408: Set Go to Memory for MOCS#0 */
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MOCS_ENTRY(0, 0, L3_1_UC | L3_GLBGO(1) | L3_LKUP(1)),
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/* UC - Coherent; GO:Memory */
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MOCS_ENTRY(1, 0, L3_1_UC | L3_GLBGO(1) | L3_LKUP(1)),
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/* UC - Non-Coherent; GO:Memory */
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MOCS_ENTRY(2, 0, L3_1_UC | L3_GLBGO(1)),
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/* WB - LC */
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MOCS_ENTRY(3, 0, L3_3_WB | L3_LKUP(1)),
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};
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static const struct xe_mocs_entry pvc_mocs_desc[] = {
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/* Error */
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MOCS_ENTRY(0, 0, L3_3_WB),
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/* UC */
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MOCS_ENTRY(1, 0, L3_1_UC),
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/* WB */
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MOCS_ENTRY(2, 0, L3_3_WB),
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};
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static const struct xe_mocs_entry mtl_mocs_desc[] = {
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/* Error - Reserved for Non-Use */
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MOCS_ENTRY(0,
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0,
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L3_LKUP(1) | L3_3_WB),
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/* Cached - L3 + L4 */
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MOCS_ENTRY(1,
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IG_PAT,
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L3_LKUP(1) | L3_3_WB),
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/* L4 - GO:L3 */
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MOCS_ENTRY(2,
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IG_PAT,
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L3_LKUP(1) | L3_1_UC),
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/* Uncached - GO:L3 */
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MOCS_ENTRY(3,
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IG_PAT | L4_3_UC,
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L3_LKUP(1) | L3_1_UC),
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/* L4 - GO:Mem */
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MOCS_ENTRY(4,
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IG_PAT,
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L3_LKUP(1) | L3_GLBGO(1) | L3_1_UC),
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/* Uncached - GO:Mem */
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MOCS_ENTRY(5,
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IG_PAT | L4_3_UC,
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L3_LKUP(1) | L3_GLBGO(1) | L3_1_UC),
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/* L4 - L3:NoLKUP; GO:L3 */
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MOCS_ENTRY(6,
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IG_PAT,
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L3_1_UC),
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/* Uncached - L3:NoLKUP; GO:L3 */
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MOCS_ENTRY(7,
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IG_PAT | L4_3_UC,
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L3_1_UC),
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/* L4 - L3:NoLKUP; GO:Mem */
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MOCS_ENTRY(8,
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IG_PAT,
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L3_GLBGO(1) | L3_1_UC),
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/* Uncached - L3:NoLKUP; GO:Mem */
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MOCS_ENTRY(9,
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IG_PAT | L4_3_UC,
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L3_GLBGO(1) | L3_1_UC),
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/* Display - L3; L4:WT */
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MOCS_ENTRY(14,
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IG_PAT | L4_1_WT,
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L3_LKUP(1) | L3_3_WB),
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/* CCS - Non-Displayable */
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MOCS_ENTRY(15,
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IG_PAT,
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L3_GLBGO(1) | L3_1_UC),
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};
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static const struct xe_mocs_entry xe2_mocs_table[] = {
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/* Defer to PAT */
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MOCS_ENTRY(0, XE2_L3_0_WB | L4_3_UC, 0),
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/* Cached L3, Uncached L4 */
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MOCS_ENTRY(1, IG_PAT | XE2_L3_0_WB | L4_3_UC, 0),
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/* Uncached L3, Cached L4 */
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MOCS_ENTRY(2, IG_PAT | XE2_L3_3_UC | L4_0_WB, 0),
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/* Uncached L3 + L4 */
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MOCS_ENTRY(3, IG_PAT | XE2_L3_3_UC | L4_3_UC, 0),
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/* Cached L3 + L4 */
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MOCS_ENTRY(4, IG_PAT | XE2_L3_0_WB | L4_0_WB, 0),
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};
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static unsigned int get_mocs_settings(struct xe_device *xe,
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struct xe_mocs_info *info)
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{
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unsigned int flags = 0;
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memset(info, 0, sizeof(struct xe_mocs_info));
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switch (xe->info.platform) {
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case XE_LUNARLAKE:
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info->size = ARRAY_SIZE(xe2_mocs_table);
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info->table = xe2_mocs_table;
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info->n_entries = XE2_NUM_MOCS_ENTRIES;
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info->uc_index = 3;
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info->wb_index = 4;
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info->unused_entries_index = 4;
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break;
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case XE_PVC:
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info->size = ARRAY_SIZE(pvc_mocs_desc);
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info->table = pvc_mocs_desc;
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info->n_entries = PVC_NUM_MOCS_ENTRIES;
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info->uc_index = 1;
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info->wb_index = 2;
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info->unused_entries_index = 2;
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break;
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case XE_METEORLAKE:
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info->size = ARRAY_SIZE(mtl_mocs_desc);
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info->table = mtl_mocs_desc;
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info->n_entries = MTL_NUM_MOCS_ENTRIES;
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info->uc_index = 9;
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info->unused_entries_index = 1;
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break;
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case XE_DG2:
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if (xe->info.subplatform == XE_SUBPLATFORM_DG2_G10 &&
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xe->info.step.graphics >= STEP_A0 &&
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xe->info.step.graphics <= STEP_B0) {
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info->size = ARRAY_SIZE(dg2_mocs_desc_g10_ax);
|
|
info->table = dg2_mocs_desc_g10_ax;
|
|
} else {
|
|
info->size = ARRAY_SIZE(dg2_mocs_desc);
|
|
info->table = dg2_mocs_desc;
|
|
}
|
|
info->uc_index = 1;
|
|
info->n_entries = XELP_NUM_MOCS_ENTRIES;
|
|
info->unused_entries_index = 3;
|
|
break;
|
|
case XE_DG1:
|
|
info->size = ARRAY_SIZE(dg1_mocs_desc);
|
|
info->table = dg1_mocs_desc;
|
|
info->uc_index = 1;
|
|
info->n_entries = XELP_NUM_MOCS_ENTRIES;
|
|
info->unused_entries_index = 5;
|
|
break;
|
|
case XE_TIGERLAKE:
|
|
case XE_ROCKETLAKE:
|
|
case XE_ALDERLAKE_S:
|
|
case XE_ALDERLAKE_P:
|
|
case XE_ALDERLAKE_N:
|
|
info->size = ARRAY_SIZE(gen12_mocs_desc);
|
|
info->table = gen12_mocs_desc;
|
|
info->n_entries = XELP_NUM_MOCS_ENTRIES;
|
|
info->uc_index = 3;
|
|
info->unused_entries_index = 2;
|
|
break;
|
|
default:
|
|
drm_err(&xe->drm, "Platform that should have a MOCS table does not.\n");
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Index 0 is a reserved/unused table entry on most platforms, but
|
|
* even on those where it does represent a legitimate MOCS entry, it
|
|
* never represents the "most cached, least coherent" behavior we want
|
|
* to populate undefined table rows with. So if unused_entries_index
|
|
* is still 0 at this point, we'll assume that it was omitted by
|
|
* mistake in the switch statement above.
|
|
*/
|
|
xe_assert(xe, info->unused_entries_index != 0);
|
|
|
|
if (XE_WARN_ON(info->size > info->n_entries)) {
|
|
info->table = NULL;
|
|
return 0;
|
|
}
|
|
|
|
if (!IS_DGFX(xe) || GRAPHICS_VER(xe) >= 20)
|
|
flags |= HAS_GLOBAL_MOCS;
|
|
if (GRAPHICS_VER(xe) < 20)
|
|
flags |= HAS_LNCF_MOCS;
|
|
|
|
return flags;
|
|
}
|
|
|
|
/*
|
|
* Get control_value from MOCS entry. If the table entry is not defined, the
|
|
* settings from unused_entries_index will be returned.
|
|
*/
|
|
static u32 get_entry_control(const struct xe_mocs_info *info,
|
|
unsigned int index)
|
|
{
|
|
if (index < info->size && info->table[index].used)
|
|
return info->table[index].control_value;
|
|
return info->table[info->unused_entries_index].control_value;
|
|
}
|
|
|
|
static void __init_mocs_table(struct xe_gt *gt,
|
|
const struct xe_mocs_info *info)
|
|
{
|
|
struct xe_device *xe = gt_to_xe(gt);
|
|
|
|
unsigned int i;
|
|
u32 mocs;
|
|
|
|
mocs_dbg(>_to_xe(gt)->drm, "entries:%d\n", info->n_entries);
|
|
drm_WARN_ONCE(&xe->drm, !info->unused_entries_index,
|
|
"Unused entries index should have been defined\n");
|
|
for (i = 0;
|
|
i < info->n_entries ? (mocs = get_entry_control(info, i)), 1 : 0;
|
|
i++) {
|
|
mocs_dbg(>_to_xe(gt)->drm, "GLOB_MOCS[%d] 0x%x 0x%x\n", i,
|
|
XELP_GLOBAL_MOCS(i).addr, mocs);
|
|
|
|
if (GRAPHICS_VERx100(gt_to_xe(gt)) > 1250)
|
|
xe_gt_mcr_multicast_write(gt, XEHP_GLOBAL_MOCS(i), mocs);
|
|
else
|
|
xe_mmio_write32(gt, XELP_GLOBAL_MOCS(i), mocs);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Get l3cc_value from MOCS entry taking into account when it's not used
|
|
* then if unused_entries_index is not zero then its value will be returned
|
|
* otherwise I915_MOCS_PTE's value is returned in this case.
|
|
*/
|
|
static u16 get_entry_l3cc(const struct xe_mocs_info *info,
|
|
unsigned int index)
|
|
{
|
|
if (index < info->size && info->table[index].used)
|
|
return info->table[index].l3cc_value;
|
|
return info->table[info->unused_entries_index].l3cc_value;
|
|
}
|
|
|
|
static u32 l3cc_combine(u16 low, u16 high)
|
|
{
|
|
return low | (u32)high << 16;
|
|
}
|
|
|
|
static void init_l3cc_table(struct xe_gt *gt,
|
|
const struct xe_mocs_info *info)
|
|
{
|
|
unsigned int i;
|
|
u32 l3cc;
|
|
|
|
mocs_dbg(>_to_xe(gt)->drm, "entries:%d\n", info->n_entries);
|
|
for (i = 0;
|
|
i < (info->n_entries + 1) / 2 ?
|
|
(l3cc = l3cc_combine(get_entry_l3cc(info, 2 * i),
|
|
get_entry_l3cc(info, 2 * i + 1))), 1 : 0;
|
|
i++) {
|
|
mocs_dbg(>_to_xe(gt)->drm, "LNCFCMOCS[%d] 0x%x 0x%x\n", i, XELP_LNCFCMOCS(i).addr,
|
|
l3cc);
|
|
|
|
if (GRAPHICS_VERx100(gt_to_xe(gt)) >= 1250)
|
|
xe_gt_mcr_multicast_write(gt, XEHP_LNCFCMOCS(i), l3cc);
|
|
else
|
|
xe_mmio_write32(gt, XELP_LNCFCMOCS(i), l3cc);
|
|
}
|
|
}
|
|
|
|
void xe_mocs_init_early(struct xe_gt *gt)
|
|
{
|
|
struct xe_mocs_info table;
|
|
|
|
get_mocs_settings(gt_to_xe(gt), &table);
|
|
gt->mocs.uc_index = table.uc_index;
|
|
gt->mocs.wb_index = table.wb_index;
|
|
}
|
|
|
|
void xe_mocs_init(struct xe_gt *gt)
|
|
{
|
|
struct xe_mocs_info table;
|
|
unsigned int flags;
|
|
|
|
/*
|
|
* MOCS settings are split between "GLOB_MOCS" and/or "LNCFCMOCS"
|
|
* registers depending on platform.
|
|
*
|
|
* These registers should be programmed before GuC initialization
|
|
* since their values will affect some of the memory transactions
|
|
* performed by the GuC.
|
|
*/
|
|
flags = get_mocs_settings(gt_to_xe(gt), &table);
|
|
mocs_dbg(>_to_xe(gt)->drm, "flag:0x%x\n", flags);
|
|
|
|
if (flags & HAS_GLOBAL_MOCS)
|
|
__init_mocs_table(gt, &table);
|
|
if (flags & HAS_LNCF_MOCS)
|
|
init_l3cc_table(gt, &table);
|
|
}
|
|
|
|
#if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST)
|
|
#include "tests/xe_mocs.c"
|
|
#endif
|