69 lines
1.9 KiB
C
69 lines
1.9 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2023 Intel Corporation
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*/
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#ifndef _XE_REGS_H_
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#define _XE_REGS_H_
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#include "regs/xe_reg_defs.h"
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#define TIMESTAMP_OVERRIDE XE_REG(0x44074)
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#define TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK REG_GENMASK(15, 12)
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#define TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK REG_GENMASK(9, 0)
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#define PCU_IRQ_OFFSET 0x444e0
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#define GU_MISC_IRQ_OFFSET 0x444f0
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#define GU_MISC_GSE REG_BIT(27)
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#define SOFTWARE_FLAGS_SPR33 XE_REG(0x4f084)
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#define GU_CNTL_PROTECTED XE_REG(0x10100C)
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#define DRIVERINT_FLR_DIS REG_BIT(31)
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#define GU_CNTL XE_REG(0x101010)
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#define LMEM_INIT REG_BIT(7)
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#define DRIVERFLR REG_BIT(31)
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#define GU_DEBUG XE_REG(0x101018)
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#define DRIVERFLR_STATUS REG_BIT(31)
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#define XEHP_CLOCK_GATE_DIS XE_REG(0x101014)
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#define SGSI_SIDECLK_DIS REG_BIT(17)
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#define GGC XE_REG(0x108040)
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#define GMS_MASK REG_GENMASK(15, 8)
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#define GGMS_MASK REG_GENMASK(7, 6)
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#define DSMBASE XE_REG(0x1080C0)
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#define BDSM_MASK REG_GENMASK64(63, 20)
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#define GSMBASE XE_REG(0x108100)
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#define STOLEN_RESERVED XE_REG(0x1082c0)
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#define WOPCM_SIZE_MASK REG_GENMASK64(9, 7)
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#define MTL_RP_STATE_CAP XE_REG(0x138000)
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#define MTL_GT_RPE_FREQUENCY XE_REG(0x13800c)
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#define MTL_MEDIAP_STATE_CAP XE_REG(0x138020)
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#define MTL_RPN_CAP_MASK REG_GENMASK(24, 16)
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#define MTL_RP0_CAP_MASK REG_GENMASK(8, 0)
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#define MTL_MPE_FREQUENCY XE_REG(0x13802c)
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#define MTL_RPE_MASK REG_GENMASK(8, 0)
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#define DG1_MSTR_TILE_INTR XE_REG(0x190008)
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#define DG1_MSTR_IRQ REG_BIT(31)
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#define DG1_MSTR_TILE(t) REG_BIT(t)
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#define GFX_MSTR_IRQ XE_REG(0x190010)
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#define MASTER_IRQ REG_BIT(31)
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#define GU_MISC_IRQ REG_BIT(29)
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#define DISPLAY_IRQ REG_BIT(16)
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#define GT_DW_IRQ(x) REG_BIT(x)
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#define PVC_RP_STATE_CAP XE_REG(0x281014)
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#endif
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