646 lines
16 KiB
ArmAsm
646 lines
16 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* linux/boot/head.S
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*
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* Copyright (C) 1991, 1992, 1993 Linus Torvalds
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*/
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/*
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* head.S contains the 32-bit startup code.
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*
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* NOTE!!! Startup happens at absolute address 0x00001000, which is also where
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* the page directory will exist. The startup code will be overwritten by
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* the page directory. [According to comments etc elsewhere on a compressed
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* kernel it will end up at 0x1000 + 1Mb I hope so as I assume this. - AC]
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*
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* Page 0 is deliberately kept safe, since System Management Mode code in
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* laptops may need to access the BIOS data stored there. This is also
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* useful for future device drivers that either access the BIOS via VM86
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* mode.
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*/
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/*
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* High loaded stuff by Hans Lermen & Werner Almesberger, Feb. 1996
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*/
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.code32
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.text
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#include <linux/init.h>
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#include <linux/linkage.h>
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#include <asm/segment.h>
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#include <asm/boot.h>
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#include <asm/msr.h>
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#include <asm/processor-flags.h>
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#include <asm/asm-offsets.h>
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#include <asm/bootparam.h>
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#include <asm/desc_defs.h>
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#include <asm/trapnr.h>
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#include "pgtable.h"
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/*
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* Fix alignment at 16 bytes. Following CONFIG_FUNCTION_ALIGNMENT will result
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* in assembly errors due to trying to move .org backward due to the excessive
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* alignment.
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*/
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#undef __ALIGN
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#define __ALIGN .balign 16, 0x90
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/*
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* Locally defined symbols should be marked hidden:
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*/
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.hidden _bss
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.hidden _ebss
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.hidden _end
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__HEAD
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/*
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* This macro gives the relative virtual address of X, i.e. the offset of X
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* from startup_32. This is the same as the link-time virtual address of X,
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* since startup_32 is at 0, but defining it this way tells the
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* assembler/linker that we do not want the actual run-time address of X. This
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* prevents the linker from trying to create unwanted run-time relocation
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* entries for the reference when the compressed kernel is linked as PIE.
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*
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* A reference X(%reg) will result in the link-time VA of X being stored with
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* the instruction, and a run-time R_X86_64_RELATIVE relocation entry that
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* adds the 64-bit base address where the kernel is loaded.
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*
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* Replacing it with (X-startup_32)(%reg) results in the offset being stored,
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* and no run-time relocation.
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*
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* The macro should be used as a displacement with a base register containing
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* the run-time address of startup_32 [i.e. rva(X)(%reg)], or as an immediate
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* [$ rva(X)].
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*
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* This macro can only be used from within the .head.text section, since the
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* expression requires startup_32 to be in the same section as the code being
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* assembled.
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*/
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#define rva(X) ((X) - startup_32)
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.code32
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SYM_FUNC_START(startup_32)
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/*
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* 32bit entry is 0 and it is ABI so immutable!
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* If we come here directly from a bootloader,
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* kernel(text+data+bss+brk) ramdisk, zero_page, command line
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* all need to be under the 4G limit.
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*/
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cld
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cli
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/*
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* Calculate the delta between where we were compiled to run
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* at and where we were actually loaded at. This can only be done
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* with a short local call on x86. Nothing else will tell us what
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* address we are running at. The reserved chunk of the real-mode
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* data at 0x1e4 (defined as a scratch field) are used as the stack
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* for this calculation. Only 4 bytes are needed.
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*/
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leal (BP_scratch+4)(%esi), %esp
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call 1f
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1: popl %ebp
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subl $ rva(1b), %ebp
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/* Load new GDT with the 64bit segments using 32bit descriptor */
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leal rva(gdt)(%ebp), %eax
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movl %eax, 2(%eax)
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lgdt (%eax)
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/* Load segment registers with our descriptors */
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movl $__BOOT_DS, %eax
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movl %eax, %ds
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movl %eax, %es
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movl %eax, %fs
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movl %eax, %gs
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movl %eax, %ss
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/* Setup a stack and load CS from current GDT */
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leal rva(boot_stack_end)(%ebp), %esp
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pushl $__KERNEL32_CS
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leal rva(1f)(%ebp), %eax
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pushl %eax
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lretl
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1:
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/* Setup Exception handling for SEV-ES */
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#ifdef CONFIG_AMD_MEM_ENCRYPT
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call startup32_load_idt
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#endif
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/* Make sure cpu supports long mode. */
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call verify_cpu
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testl %eax, %eax
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jnz .Lno_longmode
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/*
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* Compute the delta between where we were compiled to run at
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* and where the code will actually run at.
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*
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* %ebp contains the address we are loaded at by the boot loader and %ebx
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* contains the address where we should move the kernel image temporarily
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* for safe in-place decompression.
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*/
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#ifdef CONFIG_RELOCATABLE
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movl %ebp, %ebx
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movl BP_kernel_alignment(%esi), %eax
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decl %eax
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addl %eax, %ebx
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notl %eax
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andl %eax, %ebx
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cmpl $LOAD_PHYSICAL_ADDR, %ebx
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jae 1f
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#endif
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movl $LOAD_PHYSICAL_ADDR, %ebx
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1:
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/* Target address to relocate to for decompression */
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addl BP_init_size(%esi), %ebx
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subl $ rva(_end), %ebx
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/*
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* Prepare for entering 64 bit mode
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*/
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/* Enable PAE mode */
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movl %cr4, %eax
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orl $X86_CR4_PAE, %eax
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movl %eax, %cr4
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/*
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* Build early 4G boot pagetable
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*/
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/*
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* If SEV is active then set the encryption mask in the page tables.
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* This will ensure that when the kernel is copied and decompressed
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* it will be done so encrypted.
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*/
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xorl %edx, %edx
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#ifdef CONFIG_AMD_MEM_ENCRYPT
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call get_sev_encryption_bit
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xorl %edx, %edx
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testl %eax, %eax
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jz 1f
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subl $32, %eax /* Encryption bit is always above bit 31 */
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bts %eax, %edx /* Set encryption mask for page tables */
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/*
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* Set MSR_AMD64_SEV_ENABLED_BIT in sev_status so that
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* startup32_check_sev_cbit() will do a check. sev_enable() will
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* initialize sev_status with all the bits reported by
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* MSR_AMD_SEV_STATUS later, but only MSR_AMD64_SEV_ENABLED_BIT
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* needs to be set for now.
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*/
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movl $1, rva(sev_status)(%ebp)
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1:
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#endif
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/* Initialize Page tables to 0 */
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leal rva(pgtable)(%ebx), %edi
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xorl %eax, %eax
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movl $(BOOT_INIT_PGT_SIZE/4), %ecx
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rep stosl
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/* Build Level 4 */
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leal rva(pgtable + 0)(%ebx), %edi
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leal 0x1007 (%edi), %eax
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movl %eax, 0(%edi)
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addl %edx, 4(%edi)
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/* Build Level 3 */
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leal rva(pgtable + 0x1000)(%ebx), %edi
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leal 0x1007(%edi), %eax
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movl $4, %ecx
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1: movl %eax, 0x00(%edi)
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addl %edx, 0x04(%edi)
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addl $0x00001000, %eax
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addl $8, %edi
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decl %ecx
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jnz 1b
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/* Build Level 2 */
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leal rva(pgtable + 0x2000)(%ebx), %edi
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movl $0x00000183, %eax
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movl $2048, %ecx
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1: movl %eax, 0(%edi)
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addl %edx, 4(%edi)
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addl $0x00200000, %eax
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addl $8, %edi
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decl %ecx
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jnz 1b
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/* Enable the boot page tables */
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leal rva(pgtable)(%ebx), %eax
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movl %eax, %cr3
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/* Enable Long mode in EFER (Extended Feature Enable Register) */
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movl $MSR_EFER, %ecx
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rdmsr
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btsl $_EFER_LME, %eax
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wrmsr
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/* After gdt is loaded */
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xorl %eax, %eax
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lldt %ax
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movl $__BOOT_TSS, %eax
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ltr %ax
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#ifdef CONFIG_AMD_MEM_ENCRYPT
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/* Check if the C-bit position is correct when SEV is active */
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call startup32_check_sev_cbit
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#endif
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/*
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* Setup for the jump to 64bit mode
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*
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* When the jump is performed we will be in long mode but
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* in 32bit compatibility mode with EFER.LME = 1, CS.L = 0, CS.D = 1
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* (and in turn EFER.LMA = 1). To jump into 64bit mode we use
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* the new gdt/idt that has __KERNEL_CS with CS.L = 1.
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* We place all of the values on our mini stack so lret can
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* used to perform that far jump.
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*/
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leal rva(startup_64)(%ebp), %eax
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#ifdef CONFIG_EFI_MIXED
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cmpb $1, rva(efi_is64)(%ebp)
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je 1f
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leal rva(startup_64_mixed_mode)(%ebp), %eax
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1:
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#endif
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pushl $__KERNEL_CS
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pushl %eax
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/* Enter paged protected Mode, activating Long Mode */
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movl $CR0_STATE, %eax
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movl %eax, %cr0
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/* Jump from 32bit compatibility mode into 64bit mode. */
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lret
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SYM_FUNC_END(startup_32)
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.code64
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.org 0x200
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SYM_CODE_START(startup_64)
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/*
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* 64bit entry is 0x200 and it is ABI so immutable!
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* We come here either from startup_32 or directly from a
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* 64bit bootloader.
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* If we come here from a bootloader, kernel(text+data+bss+brk),
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* ramdisk, zero_page, command line could be above 4G.
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* We depend on an identity mapped page table being provided
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* that maps our entire kernel(text+data+bss+brk), zero page
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* and command line.
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*/
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cld
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cli
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/* Setup data segments. */
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xorl %eax, %eax
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movl %eax, %ds
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movl %eax, %es
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movl %eax, %ss
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movl %eax, %fs
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movl %eax, %gs
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/*
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* Compute the decompressed kernel start address. It is where
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* we were loaded at aligned to a 2M boundary. %rbp contains the
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* decompressed kernel start address.
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*
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* If it is a relocatable kernel then decompress and run the kernel
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* from load address aligned to 2MB addr, otherwise decompress and
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* run the kernel from LOAD_PHYSICAL_ADDR
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*
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* We cannot rely on the calculation done in 32-bit mode, since we
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* may have been invoked via the 64-bit entry point.
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*/
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/* Start with the delta to where the kernel will run at. */
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#ifdef CONFIG_RELOCATABLE
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leaq startup_32(%rip) /* - $startup_32 */, %rbp
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movl BP_kernel_alignment(%rsi), %eax
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decl %eax
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addq %rax, %rbp
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notq %rax
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andq %rax, %rbp
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cmpq $LOAD_PHYSICAL_ADDR, %rbp
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jae 1f
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#endif
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movq $LOAD_PHYSICAL_ADDR, %rbp
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1:
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/* Target address to relocate to for decompression */
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movl BP_init_size(%rsi), %ebx
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subl $ rva(_end), %ebx
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addq %rbp, %rbx
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/* Set up the stack */
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leaq rva(boot_stack_end)(%rbx), %rsp
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/*
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* At this point we are in long mode with 4-level paging enabled,
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* but we might want to enable 5-level paging or vice versa.
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*
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* The problem is that we cannot do it directly. Setting or clearing
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* CR4.LA57 in long mode would trigger #GP. So we need to switch off
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* long mode and paging first.
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*
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* We also need a trampoline in lower memory to switch over from
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* 4- to 5-level paging for cases when the bootloader puts the kernel
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* above 4G, but didn't enable 5-level paging for us.
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*
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* The same trampoline can be used to switch from 5- to 4-level paging
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* mode, like when starting 4-level paging kernel via kexec() when
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* original kernel worked in 5-level paging mode.
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*
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* For the trampoline, we need the top page table to reside in lower
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* memory as we don't have a way to load 64-bit values into CR3 in
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* 32-bit mode.
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*/
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/* Make sure we have GDT with 32-bit code segment */
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leaq gdt64(%rip), %rax
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addq %rax, 2(%rax)
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lgdt (%rax)
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/* Reload CS so IRET returns to a CS actually in the GDT */
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pushq $__KERNEL_CS
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leaq .Lon_kernel_cs(%rip), %rax
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pushq %rax
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lretq
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.Lon_kernel_cs:
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/*
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* RSI holds a pointer to a boot_params structure provided by the
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* loader, and this needs to be preserved across C function calls. So
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* move it into a callee saved register.
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*/
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movq %rsi, %r15
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call load_stage1_idt
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#ifdef CONFIG_AMD_MEM_ENCRYPT
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/*
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* Now that the stage1 interrupt handlers are set up, #VC exceptions from
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* CPUID instructions can be properly handled for SEV-ES guests.
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*
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* For SEV-SNP, the CPUID table also needs to be set up in advance of any
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* CPUID instructions being issued, so go ahead and do that now via
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* sev_enable(), which will also handle the rest of the SEV-related
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* detection/setup to ensure that has been done in advance of any dependent
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* code. Pass the boot_params pointer as the first argument.
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*/
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movq %r15, %rdi
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call sev_enable
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#endif
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/*
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* configure_5level_paging() updates the number of paging levels using
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* a trampoline in 32-bit addressable memory if the current number does
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* not match the desired number.
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*
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* Pass the boot_params pointer as the first argument. The second
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* argument is the relocated address of the page table to use instead
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* of the page table in trampoline memory (if required).
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*/
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movq %r15, %rdi
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leaq rva(top_pgtable)(%rbx), %rsi
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call configure_5level_paging
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/* Zero EFLAGS */
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pushq $0
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popfq
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/*
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* Copy the compressed kernel to the end of our buffer
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* where decompression in place becomes safe.
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*/
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leaq (_bss-8)(%rip), %rsi
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leaq rva(_bss-8)(%rbx), %rdi
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movl $(_bss - startup_32), %ecx
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shrl $3, %ecx
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std
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rep movsq
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cld
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/*
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* The GDT may get overwritten either during the copy we just did or
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* during extract_kernel below. To avoid any issues, repoint the GDTR
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* to the new copy of the GDT.
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*/
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leaq rva(gdt64)(%rbx), %rax
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leaq rva(gdt)(%rbx), %rdx
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movq %rdx, 2(%rax)
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lgdt (%rax)
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/*
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* Jump to the relocated address.
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*/
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leaq rva(.Lrelocated)(%rbx), %rax
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jmp *%rax
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SYM_CODE_END(startup_64)
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.text
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SYM_FUNC_START_LOCAL_NOALIGN(.Lrelocated)
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/*
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* Clear BSS (stack is currently empty)
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*/
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xorl %eax, %eax
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leaq _bss(%rip), %rdi
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leaq _ebss(%rip), %rcx
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subq %rdi, %rcx
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shrq $3, %rcx
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rep stosq
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call load_stage2_idt
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/* Pass boot_params to initialize_identity_maps() */
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movq %r15, %rdi
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call initialize_identity_maps
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/*
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* Do the extraction, and jump to the new kernel..
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*/
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/* pass struct boot_params pointer and output target address */
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movq %r15, %rdi
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movq %rbp, %rsi
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call extract_kernel /* returns kernel entry point in %rax */
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/*
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* Jump to the decompressed kernel.
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*/
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movq %r15, %rsi
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jmp *%rax
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SYM_FUNC_END(.Lrelocated)
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/*
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* This is the 32-bit trampoline that will be copied over to low memory. It
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* will be called using the ordinary 64-bit calling convention from code
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* running in 64-bit mode.
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*
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* Return address is at the top of the stack (might be above 4G).
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* The first argument (EDI) contains the address of the temporary PGD level
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* page table in 32-bit addressable memory which will be programmed into
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* register CR3.
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*/
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.section ".rodata", "a", @progbits
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SYM_CODE_START(trampoline_32bit_src)
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/*
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* Preserve callee save 64-bit registers on the stack: this is
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* necessary because the architecture does not guarantee that GPRs will
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* retain their full 64-bit values across a 32-bit mode switch.
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*/
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pushq %r15
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pushq %r14
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pushq %r13
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pushq %r12
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pushq %rbp
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pushq %rbx
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/* Preserve top half of RSP in a legacy mode GPR to avoid truncation */
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movq %rsp, %rbx
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shrq $32, %rbx
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/* Switch to compatibility mode (CS.L = 0 CS.D = 1) via far return */
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pushq $__KERNEL32_CS
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leaq 0f(%rip), %rax
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pushq %rax
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lretq
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/*
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* The 32-bit code below will do a far jump back to long mode and end
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* up here after reconfiguring the number of paging levels. First, the
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* stack pointer needs to be restored to its full 64-bit value before
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|
* the callee save register contents can be popped from the stack.
|
|
*/
|
|
.Lret:
|
|
shlq $32, %rbx
|
|
orq %rbx, %rsp
|
|
|
|
/* Restore the preserved 64-bit registers */
|
|
popq %rbx
|
|
popq %rbp
|
|
popq %r12
|
|
popq %r13
|
|
popq %r14
|
|
popq %r15
|
|
retq
|
|
|
|
.code32
|
|
0:
|
|
/* Disable paging */
|
|
movl %cr0, %eax
|
|
btrl $X86_CR0_PG_BIT, %eax
|
|
movl %eax, %cr0
|
|
|
|
/* Point CR3 to the trampoline's new top level page table */
|
|
movl %edi, %cr3
|
|
|
|
/* Set EFER.LME=1 as a precaution in case hypervsior pulls the rug */
|
|
movl $MSR_EFER, %ecx
|
|
rdmsr
|
|
btsl $_EFER_LME, %eax
|
|
/* Avoid writing EFER if no change was made (for TDX guest) */
|
|
jc 1f
|
|
wrmsr
|
|
1:
|
|
/* Toggle CR4.LA57 */
|
|
movl %cr4, %eax
|
|
btcl $X86_CR4_LA57_BIT, %eax
|
|
movl %eax, %cr4
|
|
|
|
/* Enable paging again. */
|
|
movl %cr0, %eax
|
|
btsl $X86_CR0_PG_BIT, %eax
|
|
movl %eax, %cr0
|
|
|
|
/*
|
|
* Return to the 64-bit calling code using LJMP rather than LRET, to
|
|
* avoid the need for a 32-bit addressable stack. The destination
|
|
* address will be adjusted after the template code is copied into a
|
|
* 32-bit addressable buffer.
|
|
*/
|
|
.Ljmp: ljmpl $__KERNEL_CS, $(.Lret - trampoline_32bit_src)
|
|
SYM_CODE_END(trampoline_32bit_src)
|
|
|
|
/*
|
|
* This symbol is placed right after trampoline_32bit_src() so its address can
|
|
* be used to infer the size of the trampoline code.
|
|
*/
|
|
SYM_DATA(trampoline_ljmp_imm_offset, .word .Ljmp + 1 - trampoline_32bit_src)
|
|
|
|
/*
|
|
* The trampoline code has a size limit.
|
|
* Make sure we fail to compile if the trampoline code grows
|
|
* beyond TRAMPOLINE_32BIT_CODE_SIZE bytes.
|
|
*/
|
|
.org trampoline_32bit_src + TRAMPOLINE_32BIT_CODE_SIZE
|
|
|
|
.text
|
|
SYM_FUNC_START_LOCAL_NOALIGN(.Lno_longmode)
|
|
/* This isn't an x86-64 CPU, so hang intentionally, we cannot continue */
|
|
1:
|
|
hlt
|
|
jmp 1b
|
|
SYM_FUNC_END(.Lno_longmode)
|
|
|
|
.globl verify_cpu
|
|
#include "../../kernel/verify_cpu.S"
|
|
|
|
.data
|
|
SYM_DATA_START_LOCAL(gdt64)
|
|
.word gdt_end - gdt - 1
|
|
.quad gdt - gdt64
|
|
SYM_DATA_END(gdt64)
|
|
.balign 8
|
|
SYM_DATA_START_LOCAL(gdt)
|
|
.word gdt_end - gdt - 1
|
|
.long 0
|
|
.word 0
|
|
.quad 0x00cf9a000000ffff /* __KERNEL32_CS */
|
|
.quad 0x00af9a000000ffff /* __KERNEL_CS */
|
|
.quad 0x00cf92000000ffff /* __KERNEL_DS */
|
|
.quad 0x0080890000000000 /* TS descriptor */
|
|
.quad 0x0000000000000000 /* TS continued */
|
|
SYM_DATA_END_LABEL(gdt, SYM_L_LOCAL, gdt_end)
|
|
|
|
SYM_DATA_START(boot_idt_desc)
|
|
.word boot_idt_end - boot_idt - 1
|
|
.quad 0
|
|
SYM_DATA_END(boot_idt_desc)
|
|
.balign 8
|
|
SYM_DATA_START(boot_idt)
|
|
.rept BOOT_IDT_ENTRIES
|
|
.quad 0
|
|
.quad 0
|
|
.endr
|
|
SYM_DATA_END_LABEL(boot_idt, SYM_L_GLOBAL, boot_idt_end)
|
|
|
|
/*
|
|
* Stack and heap for uncompression
|
|
*/
|
|
.bss
|
|
.balign 4
|
|
SYM_DATA_START_LOCAL(boot_stack)
|
|
.fill BOOT_STACK_SIZE, 1, 0
|
|
.balign 16
|
|
SYM_DATA_END_LABEL(boot_stack, SYM_L_LOCAL, boot_stack_end)
|
|
|
|
/*
|
|
* Space for page tables (not in .bss so not zeroed)
|
|
*/
|
|
.section ".pgtable","aw",@nobits
|
|
.balign 4096
|
|
SYM_DATA_LOCAL(pgtable, .fill BOOT_PGT_SIZE, 1, 0)
|
|
|
|
/*
|
|
* The page table is going to be used instead of page table in the trampoline
|
|
* memory.
|
|
*/
|
|
SYM_DATA_LOCAL(top_pgtable, .fill PAGE_SIZE, 1, 0)
|