916 lines
21 KiB
Plaintext
916 lines
21 KiB
Plaintext
// SPDX-License-Identifier: BSD-3-Clause
|
|
/*
|
|
* SDX75 SoC device tree source
|
|
*
|
|
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
|
*
|
|
*/
|
|
|
|
#include <dt-bindings/clock/qcom,rpmh.h>
|
|
#include <dt-bindings/clock/qcom,sdx75-gcc.h>
|
|
#include <dt-bindings/interconnect/qcom,icc.h>
|
|
#include <dt-bindings/interconnect/qcom,sdx75.h>
|
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
|
#include <dt-bindings/power/qcom,rpmhpd.h>
|
|
#include <dt-bindings/power/qcom-rpmpd.h>
|
|
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
|
|
|
|
/ {
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
interrupt-parent = <&intc>;
|
|
|
|
chosen: chosen { };
|
|
|
|
clocks {
|
|
xo_board: xo-board {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <76800000>;
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
sleep_clk: sleep-clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <32000>;
|
|
#clock-cells = <0>;
|
|
};
|
|
};
|
|
|
|
cpus {
|
|
#address-cells = <2>;
|
|
#size-cells = <0>;
|
|
|
|
CPU0: cpu@0 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a55";
|
|
reg = <0x0 0x0>;
|
|
clocks = <&cpufreq_hw 0>;
|
|
enable-method = "psci";
|
|
power-domains = <&CPU_PD0>;
|
|
power-domain-names = "psci";
|
|
qcom,freq-domain = <&cpufreq_hw 0>;
|
|
capacity-dmips-mhz = <1024>;
|
|
dynamic-power-coefficient = <100>;
|
|
next-level-cache = <&L2_0>;
|
|
|
|
L2_0: l2-cache {
|
|
compatible = "cache";
|
|
cache-level = <2>;
|
|
cache-unified;
|
|
next-level-cache = <&L3_0>;
|
|
L3_0: l3-cache {
|
|
compatible = "cache";
|
|
cache-level = <3>;
|
|
cache-unified;
|
|
};
|
|
};
|
|
};
|
|
|
|
CPU1: cpu@100 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a55";
|
|
reg = <0x0 0x100>;
|
|
clocks = <&cpufreq_hw 0>;
|
|
enable-method = "psci";
|
|
power-domains = <&CPU_PD1>;
|
|
power-domain-names = "psci";
|
|
qcom,freq-domain = <&cpufreq_hw 0>;
|
|
capacity-dmips-mhz = <1024>;
|
|
dynamic-power-coefficient = <100>;
|
|
next-level-cache = <&L2_100>;
|
|
|
|
L2_100: l2-cache {
|
|
compatible = "cache";
|
|
cache-level = <2>;
|
|
cache-unified;
|
|
next-level-cache = <&L3_0>;
|
|
};
|
|
};
|
|
|
|
CPU2: cpu@200 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a55";
|
|
reg = <0x0 0x200>;
|
|
clocks = <&cpufreq_hw 0>;
|
|
enable-method = "psci";
|
|
power-domains = <&CPU_PD2>;
|
|
power-domain-names = "psci";
|
|
qcom,freq-domain = <&cpufreq_hw 0>;
|
|
capacity-dmips-mhz = <1024>;
|
|
dynamic-power-coefficient = <100>;
|
|
next-level-cache = <&L2_200>;
|
|
|
|
L2_200: l2-cache {
|
|
compatible = "cache";
|
|
cache-level = <2>;
|
|
cache-unified;
|
|
next-level-cache = <&L3_0>;
|
|
};
|
|
};
|
|
|
|
CPU3: cpu@300 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a55";
|
|
reg = <0x0 0x300>;
|
|
clocks = <&cpufreq_hw 0>;
|
|
enable-method = "psci";
|
|
power-domains = <&CPU_PD3>;
|
|
power-domain-names = "psci";
|
|
qcom,freq-domain = <&cpufreq_hw 0>;
|
|
capacity-dmips-mhz = <1024>;
|
|
dynamic-power-coefficient = <100>;
|
|
next-level-cache = <&L2_300>;
|
|
|
|
L2_300: l2-cache {
|
|
compatible = "cache";
|
|
cache-level = <2>;
|
|
cache-unified;
|
|
next-level-cache = <&L3_0>;
|
|
};
|
|
};
|
|
|
|
cpu-map {
|
|
cluster0 {
|
|
core0 {
|
|
cpu = <&CPU0>;
|
|
};
|
|
|
|
core1 {
|
|
cpu = <&CPU1>;
|
|
};
|
|
|
|
core2 {
|
|
cpu = <&CPU2>;
|
|
};
|
|
|
|
core3 {
|
|
cpu = <&CPU3>;
|
|
};
|
|
};
|
|
};
|
|
|
|
idle-states {
|
|
entry-method = "psci";
|
|
|
|
CPU_OFF: cpu-sleep-0 {
|
|
compatible = "arm,idle-state";
|
|
entry-latency-us = <235>;
|
|
exit-latency-us = <428>;
|
|
min-residency-us = <1774>;
|
|
arm,psci-suspend-param = <0x40000003>;
|
|
local-timer-stop;
|
|
};
|
|
|
|
CPU_RAIL_OFF: cpu-rail-sleep-1 {
|
|
compatible = "arm,idle-state";
|
|
entry-latency-us = <800>;
|
|
exit-latency-us = <750>;
|
|
min-residency-us = <4090>;
|
|
arm,psci-suspend-param = <0x40000004>;
|
|
local-timer-stop;
|
|
};
|
|
|
|
};
|
|
|
|
domain-idle-states {
|
|
CLUSTER_SLEEP_0: cluster-sleep-0 {
|
|
compatible = "domain-idle-state";
|
|
arm,psci-suspend-param = <0x41000044>;
|
|
entry-latency-us = <1050>;
|
|
exit-latency-us = <2500>;
|
|
min-residency-us = <5309>;
|
|
};
|
|
|
|
CLUSTER_SLEEP_1: cluster-sleep-1 {
|
|
compatible = "domain-idle-state";
|
|
arm,psci-suspend-param = <0x41001344>;
|
|
entry-latency-us = <2761>;
|
|
exit-latency-us = <3964>;
|
|
min-residency-us = <8467>;
|
|
};
|
|
|
|
CLUSTER_SLEEP_2: cluster-sleep-2 {
|
|
compatible = "domain-idle-state";
|
|
arm,psci-suspend-param = <0x4100b344>;
|
|
entry-latency-us = <2793>;
|
|
exit-latency-us = <4023>;
|
|
min-residency-us = <9826>;
|
|
};
|
|
};
|
|
};
|
|
|
|
firmware {
|
|
scm: scm {
|
|
compatible = "qcom,scm-sdx75", "qcom,scm";
|
|
};
|
|
};
|
|
|
|
clk_virt: interconnect-0 {
|
|
compatible = "qcom,sdx75-clk-virt";
|
|
#interconnect-cells = <2>;
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
clocks = <&rpmhcc RPMH_QPIC_CLK>;
|
|
};
|
|
|
|
mc_virt: interconnect-1 {
|
|
compatible = "qcom,sdx75-mc-virt";
|
|
#interconnect-cells = <2>;
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
memory@80000000 {
|
|
device_type = "memory";
|
|
reg = <0x0 0x80000000 0x0 0x0>;
|
|
};
|
|
|
|
pmu {
|
|
compatible = "arm,armv8-pmuv3";
|
|
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
psci {
|
|
compatible = "arm,psci-1.0";
|
|
method = "smc";
|
|
|
|
CPU_PD0: power-domain-cpu0 {
|
|
#power-domain-cells = <0>;
|
|
power-domains = <&CLUSTER_PD>;
|
|
domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>;
|
|
};
|
|
|
|
CPU_PD1: power-domain-cpu1 {
|
|
#power-domain-cells = <0>;
|
|
power-domains = <&CLUSTER_PD>;
|
|
domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>;
|
|
};
|
|
|
|
CPU_PD2: power-domain-cpu2 {
|
|
#power-domain-cells = <0>;
|
|
power-domains = <&CLUSTER_PD>;
|
|
domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>;
|
|
};
|
|
|
|
CPU_PD3: power-domain-cpu3 {
|
|
#power-domain-cells = <0>;
|
|
power-domains = <&CLUSTER_PD>;
|
|
domain-idle-states = <&CPU_OFF &CPU_RAIL_OFF>;
|
|
};
|
|
|
|
CLUSTER_PD: power-domain-cpu-cluster0 {
|
|
#power-domain-cells = <0>;
|
|
domain-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_1 &CLUSTER_SLEEP_2>;
|
|
};
|
|
};
|
|
|
|
reserved-memory {
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
|
|
gunyah_hyp_mem: gunyah-hyp@80000000 {
|
|
reg = <0x0 0x80000000 0x0 0x800000>;
|
|
no-map;
|
|
};
|
|
|
|
hyp_elf_package_mem: hyp-elf-package@80800000 {
|
|
reg = <0x0 0x80800000 0x0 0x200000>;
|
|
no-map;
|
|
};
|
|
|
|
access_control_db_mem: access-control-db@81380000 {
|
|
reg = <0x0 0x81380000 0x0 0x80000>;
|
|
no-map;
|
|
};
|
|
|
|
qteetz_mem: qteetz@814e0000 {
|
|
reg = <0x0 0x814e0000 0x0 0x2a0000>;
|
|
no-map;
|
|
};
|
|
|
|
trusted_apps_mem: trusted-apps@81780000 {
|
|
reg = <0x0 0x81780000 0x0 0xa00000>;
|
|
no-map;
|
|
};
|
|
|
|
xbl_ramdump_mem: xbl-ramdump@87a00000 {
|
|
reg = <0x0 0x87a00000 0x0 0x1c0000>;
|
|
no-map;
|
|
};
|
|
|
|
cpucp_fw_mem: cpucp-fw@87c00000 {
|
|
reg = <0x0 0x87c00000 0x0 0x100000>;
|
|
no-map;
|
|
};
|
|
|
|
xbl_dtlog_mem: xbl-dtlog@87d00000 {
|
|
reg = <0x0 0x87d00000 0x0 0x40000>;
|
|
no-map;
|
|
};
|
|
|
|
xbl_sc_mem: xbl-sc@87d40000 {
|
|
reg = <0x0 0x87d40000 0x0 0x40000>;
|
|
no-map;
|
|
};
|
|
|
|
modem_efs_shared_mem: modem-efs-shared@87d80000 {
|
|
reg = <0x0 0x87d80000 0x0 0x10000>;
|
|
no-map;
|
|
};
|
|
|
|
aop_image_mem: aop-image@87e00000 {
|
|
reg = <0x0 0x87e00000 0x0 0x20000>;
|
|
no-map;
|
|
};
|
|
|
|
smem_mem: smem@87e20000 {
|
|
reg = <0x0 0x87e20000 0x0 0xc0000>;
|
|
no-map;
|
|
};
|
|
|
|
aop_cmd_db_mem: aop-cmd-db@87ee0000 {
|
|
compatible = "qcom,cmd-db";
|
|
reg = <0x0 0x87ee0000 0x0 0x20000>;
|
|
no-map;
|
|
};
|
|
|
|
aop_config_mem: aop-config@87f00000 {
|
|
reg = <0x0 0x87f00000 0x0 0x20000>;
|
|
no-map;
|
|
};
|
|
|
|
ipa_fw_mem: ipa-fw@87f20000 {
|
|
reg = <0x0 0x87f20000 0x0 0x10000>;
|
|
no-map;
|
|
};
|
|
|
|
secdata_mem: secdata@87f30000 {
|
|
reg = <0x0 0x87f30000 0x0 0x1000>;
|
|
no-map;
|
|
};
|
|
|
|
tme_crashdump_mem: tme-crashdump@87f31000 {
|
|
reg = <0x0 0x87f31000 0x0 0x40000>;
|
|
no-map;
|
|
};
|
|
|
|
tme_log_mem: tme-log@87f71000 {
|
|
reg = <0x0 0x87f71000 0x0 0x4000>;
|
|
no-map;
|
|
};
|
|
|
|
uefi_log_mem: uefi-log@87f75000 {
|
|
reg = <0x0 0x87f75000 0x0 0x10000>;
|
|
no-map;
|
|
};
|
|
|
|
qdss_mem: qdss@88800000 {
|
|
reg = <0x0 0x88800000 0x0 0x300000>;
|
|
no-map;
|
|
};
|
|
|
|
audio_heap_mem: audio-heap@88b00000 {
|
|
compatible = "shared-dma-pool";
|
|
reg = <0x0 0x88b00000 0x0 0x400000>;
|
|
no-map;
|
|
};
|
|
|
|
mpss_dsmharq_mem: mpss-dsmharq@88f00000 {
|
|
reg = <0x0 0x88f00000 0x0 0x5080000>;
|
|
no-map;
|
|
};
|
|
|
|
q6_mpss_dtb_mem: q6-mpss-dtb@8df80000 {
|
|
reg = <0x0 0x8df80000 0x0 0x80000>;
|
|
no-map;
|
|
};
|
|
|
|
mpssadsp_mem: mpssadsp@8e000000 {
|
|
reg = <0x0 0x8e000000 0x0 0xf400000>;
|
|
no-map;
|
|
};
|
|
|
|
gunyah_trace_buffer_mem: gunyah-trace-buffer@bdb00000 {
|
|
reg = <0x0 0xbdb00000 0x0 0x2000000>;
|
|
no-map;
|
|
};
|
|
|
|
smmu_debug_buf_mem: smmu-debug-buf@bfb00000 {
|
|
reg = <0x0 0xbfb00000 0x0 0x100000>;
|
|
no-map;
|
|
};
|
|
|
|
hyp_smmu_s2_pt_mem: hyp-smmu-s2-pt@bfc00000 {
|
|
reg = <0x0 0xbfc00000 0x0 0x400000>;
|
|
no-map;
|
|
};
|
|
};
|
|
|
|
smem: qcom,smem {
|
|
compatible = "qcom,smem";
|
|
memory-region = <&smem_mem>;
|
|
hwlocks = <&tcsr_mutex 3>;
|
|
};
|
|
|
|
soc: soc {
|
|
compatible = "simple-bus";
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges = <0 0 0 0 0x10 0>;
|
|
dma-ranges = <0 0 0 0 0x10 0>;
|
|
|
|
gcc: clock-controller@80000 {
|
|
compatible = "qcom,sdx75-gcc";
|
|
reg = <0x0 0x0080000 0x0 0x1f7400>;
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
|
<&sleep_clk>,
|
|
<0>,
|
|
<0>,
|
|
<0>,
|
|
<0>,
|
|
<0>,
|
|
<0>,
|
|
<0>,
|
|
<0>,
|
|
<0>,
|
|
<0>,
|
|
<0>,
|
|
<0>,
|
|
<0>;
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
#power-domain-cells = <1>;
|
|
};
|
|
|
|
qupv3_id_0: geniqup@9c0000 {
|
|
compatible = "qcom,geni-se-qup";
|
|
reg = <0x0 0x009c0000 0x0 0x2000>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
|
|
clock-names = "m-ahb",
|
|
"s-ahb";
|
|
iommus = <&apps_smmu 0xe3 0x0>;
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core";
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
status = "disabled";
|
|
|
|
uart1: serial@984000 {
|
|
compatible = "qcom,geni-debug-uart";
|
|
reg = <0x0 0x00984000 0x0 0x4000>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
|
|
clock-names = "se";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config";
|
|
interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>;
|
|
pinctrl-0 = <&qupv3_se1_2uart_active>;
|
|
pinctrl-1 = <&qupv3_se1_2uart_sleep>;
|
|
pinctrl-names = "default",
|
|
"sleep";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
usb_hsphy: phy@ff4000 {
|
|
compatible = "qcom,sdx75-snps-eusb2-phy", "qcom,sm8550-snps-eusb2-phy";
|
|
reg = <0x0 0x00ff4000 0x0 0x154>;
|
|
#phy-cells = <0>;
|
|
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
|
clock-names = "ref";
|
|
|
|
resets = <&gcc GCC_QUSB2PHY_BCR>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
usb_qmpphy: phy@ff6000 {
|
|
compatible = "qcom,sdx75-qmp-usb3-uni-phy";
|
|
reg = <0x0 0x00ff6000 0x0 0x2000>;
|
|
|
|
clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
|
|
<&gcc GCC_USB2_CLKREF_EN>,
|
|
<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
|
|
<&gcc GCC_USB3_PHY_PIPE_CLK>;
|
|
clock-names = "aux",
|
|
"ref",
|
|
"cfg_ahb",
|
|
"pipe";
|
|
|
|
power-domains = <&gcc GCC_USB3_PHY_GDSC>;
|
|
|
|
resets = <&gcc GCC_USB3_PHY_BCR>,
|
|
<&gcc GCC_USB3PHY_PHY_BCR>;
|
|
reset-names = "phy",
|
|
"phy_phy";
|
|
|
|
#clock-cells = <0>;
|
|
clock-output-names = "usb3_uni_phy_pipe_clk_src";
|
|
|
|
#phy-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
system_noc: interconnect@1640000 {
|
|
compatible = "qcom,sdx75-system-noc";
|
|
reg = <0x0 0x01640000 0x0 0x4b400>;
|
|
#interconnect-cells = <2>;
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
pcie_anoc: interconnect@16c0000 {
|
|
compatible = "qcom,sdx75-pcie-anoc";
|
|
reg = <0x0 0x016c0000 0x0 0x14200>;
|
|
#interconnect-cells = <2>;
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
tcsr_mutex: hwlock@1f40000 {
|
|
compatible = "qcom,tcsr-mutex";
|
|
reg = <0x0 0x01f40000 0x0 0x40000>;
|
|
#hwlock-cells = <1>;
|
|
};
|
|
|
|
usb: usb@a6f8800 {
|
|
compatible = "qcom,sdx75-dwc3", "qcom,dwc3";
|
|
reg = <0x0 0x0a6f8800 0x0 0x400>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
|
|
clocks = <&gcc GCC_USB30_SLV_AHB_CLK>,
|
|
<&gcc GCC_USB30_MASTER_CLK>,
|
|
<&gcc GCC_USB30_MSTR_AXI_CLK>,
|
|
<&gcc GCC_USB30_SLEEP_CLK>,
|
|
<&gcc GCC_USB30_MOCK_UTMI_CLK>;
|
|
clock-names = "cfg_noc",
|
|
"core",
|
|
"iface",
|
|
"sleep",
|
|
"mock_utmi";
|
|
|
|
assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
|
|
<&gcc GCC_USB30_MASTER_CLK>;
|
|
assigned-clock-rates = <19200000>, <200000000>;
|
|
|
|
interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
|
|
<&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
|
|
<&pdc 9 IRQ_TYPE_EDGE_RISING>,
|
|
<&pdc 10 IRQ_TYPE_EDGE_RISING>;
|
|
interrupt-names = "hs_phy_irq",
|
|
"ss_phy_irq",
|
|
"dm_hs_phy_irq",
|
|
"dp_hs_phy_irq";
|
|
|
|
power-domains = <&gcc GCC_USB30_GDSC>;
|
|
|
|
resets = <&gcc GCC_USB30_BCR>;
|
|
|
|
interconnects = <&system_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&system_noc SLAVE_USB3 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "usb-ddr",
|
|
"apps-usb";
|
|
|
|
status = "disabled";
|
|
|
|
usb_dwc3: usb@a600000 {
|
|
compatible = "snps,dwc3";
|
|
reg = <0x0 0x0a600000 0x0 0xcd00>;
|
|
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
|
|
iommus = <&apps_smmu 0x80 0x0>;
|
|
snps,dis_u2_susphy_quirk;
|
|
snps,dis_enblslpm_quirk;
|
|
phys = <&usb_hsphy>,
|
|
<&usb_qmpphy>;
|
|
phy-names = "usb2-phy",
|
|
"usb3-phy";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
|
|
usb_1_dwc3_hs: endpoint {
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
|
|
usb_1_dwc3_ss: endpoint {
|
|
};
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
pdc: interrupt-controller@b220000 {
|
|
compatible = "qcom,sdx75-pdc", "qcom,pdc";
|
|
reg = <0x0 0xb220000 0x0 0x30000>,
|
|
<0x0 0x174000f0 0x0 0x64>;
|
|
qcom,pdc-ranges = <0 147 52>,
|
|
<52 266 32>,
|
|
<84 500 59>;
|
|
#interrupt-cells = <2>;
|
|
interrupt-parent = <&intc>;
|
|
interrupt-controller;
|
|
};
|
|
|
|
spmi_bus: spmi@c400000 {
|
|
compatible = "qcom,spmi-pmic-arb";
|
|
reg = <0x0 0x0c400000 0x0 0x3000>,
|
|
<0x0 0x0c500000 0x0 0x400000>,
|
|
<0x0 0x0c440000 0x0 0x80000>,
|
|
<0x0 0x0c4c0000 0x0 0x10000>,
|
|
<0x0 0x0c42d000 0x0 0x4000>;
|
|
reg-names = "core",
|
|
"chnls",
|
|
"obsrvr",
|
|
"intr",
|
|
"cnfg";
|
|
interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "periph_irq";
|
|
qcom,ee = <0>;
|
|
qcom,channel = <0>;
|
|
qcom,bus-id = <0>;
|
|
#address-cells = <2>;
|
|
#size-cells = <0>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <4>;
|
|
};
|
|
|
|
tlmm: pinctrl@f000000 {
|
|
compatible = "qcom,sdx75-tlmm";
|
|
reg = <0x0 0x0f000000 0x0 0x400000>;
|
|
interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
gpio-ranges = <&tlmm 0 0 133>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
wakeup-parent = <&pdc>;
|
|
|
|
qupv3_se1_2uart_active: qupv3-se1-2uart-active-state {
|
|
tx-pins {
|
|
pins = "gpio12";
|
|
function = "qup_se1_l2_mira";
|
|
drive-strength = <2>;
|
|
bias-disable;
|
|
};
|
|
|
|
rx-pins {
|
|
pins = "gpio13";
|
|
function = "qup_se1_l3_mira";
|
|
drive-strength = <2>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se1_2uart_sleep: qupv3-se1-2uart-sleep-state {
|
|
pins = "gpio12", "gpio13";
|
|
function = "gpio";
|
|
drive-strength = <2>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
apps_smmu: iommu@15000000 {
|
|
compatible = "qcom,sdx75-smmu-500", "qcom,smmu-500", "arm,mmu-500";
|
|
reg = <0x0 0x15000000 0x0 0x40000>;
|
|
#iommu-cells = <2>;
|
|
#global-interrupts = <2>;
|
|
dma-coherent;
|
|
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
intc: interrupt-controller@17200000 {
|
|
compatible = "arm,gic-v3";
|
|
#interrupt-cells = <3>;
|
|
interrupt-controller;
|
|
#redistributor-regions = <1>;
|
|
redistributor-stride = <0x0 0x20000>;
|
|
reg = <0x0 0x17200000 0x0 0x10000>,
|
|
<0x0 0x17260000 0x0 0x80000>;
|
|
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
timer@17420000 {
|
|
compatible = "arm,armv7-timer-mem";
|
|
reg = <0x0 0x17420000 0x0 0x1000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0 0 0x20000000>;
|
|
|
|
frame@17421000 {
|
|
reg = <0x17421000 0x1000>,
|
|
<0x17422000 0x1000>;
|
|
frame-number = <0>;
|
|
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
frame@17423000 {
|
|
reg = <0x17423000 0x1000>;
|
|
frame-number = <1>;
|
|
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17425000 {
|
|
reg = <0x17425000 0x1000>;
|
|
frame-number = <2>;
|
|
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17427000 {
|
|
reg = <0x17427000 0x1000>;
|
|
frame-number = <3>;
|
|
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17429000 {
|
|
reg = <0x17429000 0x1000>;
|
|
frame-number = <4>;
|
|
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@1742b000 {
|
|
reg = <0x1742b000 0x1000>;
|
|
frame-number = <5>;
|
|
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@1742d000 {
|
|
reg = <0x1742d000 0x1000>;
|
|
frame-number = <6>;
|
|
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
apps_rsc: rsc@17a00000 {
|
|
label = "apps_rsc";
|
|
compatible = "qcom,rpmh-rsc";
|
|
reg = <0x0 0x17a00000 0x0 0x10000>,
|
|
<0x0 0x17a10000 0x0 0x10000>,
|
|
<0x0 0x17a20000 0x0 0x10000>;
|
|
reg-names = "drv-0", "drv-1", "drv-2";
|
|
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
power-domains = <&CLUSTER_PD>;
|
|
qcom,tcs-offset = <0xd00>;
|
|
qcom,drv-id = <2>;
|
|
qcom,tcs-config = <ACTIVE_TCS 3>,
|
|
<SLEEP_TCS 2>,
|
|
<WAKE_TCS 2>,
|
|
<CONTROL_TCS 0>;
|
|
|
|
apps_bcm_voter: bcm-voter {
|
|
compatible = "qcom,bcm-voter";
|
|
};
|
|
|
|
rpmhcc: clock-controller {
|
|
compatible = "qcom,sdx75-rpmh-clk";
|
|
clocks = <&xo_board>;
|
|
clock-names = "xo";
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
rpmhpd: power-controller {
|
|
compatible = "qcom,sdx75-rpmhpd";
|
|
#power-domain-cells = <1>;
|
|
operating-points-v2 = <&rpmhpd_opp_table>;
|
|
|
|
rpmhpd_opp_table: opp-table {
|
|
compatible = "operating-points-v2";
|
|
|
|
rpmhpd_opp_ret: opp-16 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
|
|
};
|
|
|
|
rpmhpd_opp_min_svs: opp-48 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
|
|
};
|
|
|
|
rpmhpd_opp_low_svs: opp-64 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
|
};
|
|
|
|
rpmhpd_opp_svs: opp-128 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
|
|
};
|
|
|
|
rpmhpd_opp_svs_l1: opp-192 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
|
};
|
|
|
|
rpmhpd_opp_nom: opp-256 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
|
|
};
|
|
|
|
rpmhpd_opp_nom_l1: opp-320 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
|
|
};
|
|
|
|
rpmhpd_opp_nom_l2: opp-336 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
|
|
};
|
|
|
|
rpmhpd_opp_turbo: opp-384 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
|
|
};
|
|
|
|
rpmhpd_opp_turbo_l1: opp-416 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
cpufreq_hw: cpufreq@17d91000 {
|
|
compatible = "qcom,sdx75-cpufreq-epss", "qcom,cpufreq-epss";
|
|
reg = <0x0 0x17d91000 0x0 0x1000>;
|
|
reg-names = "freq-domain0";
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
|
<&gcc GPLL0>;
|
|
clock-names = "xo",
|
|
"alternate";
|
|
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "dcvsh-irq-0";
|
|
#freq-domain-cells = <1>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
dc_noc: interconnect@190e0000 {
|
|
compatible = "qcom,sdx75-dc-noc";
|
|
reg = <0x0 0x190e0000 0x0 0x8200>;
|
|
#interconnect-cells = <2>;
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
gem_noc: interconnect@19100000 {
|
|
compatible = "qcom,sdx75-gem-noc";
|
|
reg = <0x0 0x19100000 0x0 0x34080>;
|
|
#interconnect-cells = <2>;
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv8-timer";
|
|
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
|
|
};
|
|
};
|