3718 lines
96 KiB
Plaintext
3718 lines
96 KiB
Plaintext
// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2023, Linaro Limited
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*/
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#include <dt-bindings/interconnect/qcom,icc.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/clock/qcom,sa8775p-gcc.h>
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#include <dt-bindings/clock/qcom,sa8775p-gpucc.h>
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#include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h>
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#include <dt-bindings/mailbox/qcom-ipcc.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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#include <dt-bindings/soc/qcom,rpmh-rsc.h>
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/ {
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interrupt-parent = <&intc>;
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#address-cells = <2>;
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#size-cells = <2>;
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clocks {
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xo_board_clk: xo-board-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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};
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sleep_clk: sleep-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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};
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};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x0>;
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enable-method = "psci";
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qcom,freq-domain = <&cpufreq_hw 0>;
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next-level-cache = <&L2_0>;
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L2_0: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&L3_0>;
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L3_0: l3-cache {
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compatible = "cache";
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cache-level = <3>;
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cache-unified;
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};
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};
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};
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CPU1: cpu@100 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x100>;
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enable-method = "psci";
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qcom,freq-domain = <&cpufreq_hw 0>;
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next-level-cache = <&L2_1>;
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L2_1: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&L3_0>;
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};
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};
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CPU2: cpu@200 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x200>;
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enable-method = "psci";
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qcom,freq-domain = <&cpufreq_hw 0>;
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next-level-cache = <&L2_2>;
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L2_2: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&L3_0>;
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};
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};
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CPU3: cpu@300 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x300>;
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enable-method = "psci";
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qcom,freq-domain = <&cpufreq_hw 0>;
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next-level-cache = <&L2_3>;
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L2_3: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&L3_0>;
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};
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};
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CPU4: cpu@10000 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x10000>;
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enable-method = "psci";
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qcom,freq-domain = <&cpufreq_hw 1>;
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next-level-cache = <&L2_4>;
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L2_4: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&L3_1>;
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L3_1: l3-cache {
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compatible = "cache";
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cache-level = <3>;
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cache-unified;
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};
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};
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};
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CPU5: cpu@10100 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x10100>;
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enable-method = "psci";
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qcom,freq-domain = <&cpufreq_hw 1>;
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next-level-cache = <&L2_5>;
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L2_5: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&L3_1>;
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};
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};
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CPU6: cpu@10200 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x10200>;
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enable-method = "psci";
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qcom,freq-domain = <&cpufreq_hw 1>;
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next-level-cache = <&L2_6>;
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L2_6: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&L3_1>;
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};
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};
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CPU7: cpu@10300 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x10300>;
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enable-method = "psci";
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qcom,freq-domain = <&cpufreq_hw 1>;
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next-level-cache = <&L2_7>;
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L2_7: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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next-level-cache = <&L3_1>;
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};
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};
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&CPU0>;
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};
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core1 {
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cpu = <&CPU1>;
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};
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core2 {
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cpu = <&CPU2>;
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};
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core3 {
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cpu = <&CPU3>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&CPU4>;
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};
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core1 {
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cpu = <&CPU5>;
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};
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core2 {
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cpu = <&CPU6>;
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};
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core3 {
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cpu = <&CPU7>;
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};
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};
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};
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};
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firmware {
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scm {
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compatible = "qcom,scm-sa8775p", "qcom,scm";
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};
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};
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aggre1_noc: interconnect-aggre1-noc {
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compatible = "qcom,sa8775p-aggre1-noc";
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#interconnect-cells = <2>;
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qcom,bcm-voters = <&apps_bcm_voter>;
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};
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aggre2_noc: interconnect-aggre2-noc {
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compatible = "qcom,sa8775p-aggre2-noc";
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#interconnect-cells = <2>;
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qcom,bcm-voters = <&apps_bcm_voter>;
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};
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clk_virt: interconnect-clk-virt {
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compatible = "qcom,sa8775p-clk-virt";
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#interconnect-cells = <2>;
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qcom,bcm-voters = <&apps_bcm_voter>;
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};
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config_noc: interconnect-config-noc {
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compatible = "qcom,sa8775p-config-noc";
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#interconnect-cells = <2>;
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qcom,bcm-voters = <&apps_bcm_voter>;
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};
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dc_noc: interconnect-dc-noc {
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compatible = "qcom,sa8775p-dc-noc";
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#interconnect-cells = <2>;
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qcom,bcm-voters = <&apps_bcm_voter>;
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};
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gem_noc: interconnect-gem-noc {
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compatible = "qcom,sa8775p-gem-noc";
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#interconnect-cells = <2>;
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qcom,bcm-voters = <&apps_bcm_voter>;
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};
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gpdsp_anoc: interconnect-gpdsp-anoc {
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compatible = "qcom,sa8775p-gpdsp-anoc";
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#interconnect-cells = <2>;
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qcom,bcm-voters = <&apps_bcm_voter>;
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};
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lpass_ag_noc: interconnect-lpass-ag-noc {
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compatible = "qcom,sa8775p-lpass-ag-noc";
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#interconnect-cells = <2>;
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qcom,bcm-voters = <&apps_bcm_voter>;
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};
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mc_virt: interconnect-mc-virt {
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compatible = "qcom,sa8775p-mc-virt";
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#interconnect-cells = <2>;
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qcom,bcm-voters = <&apps_bcm_voter>;
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};
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mmss_noc: interconnect-mmss-noc {
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compatible = "qcom,sa8775p-mmss-noc";
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#interconnect-cells = <2>;
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qcom,bcm-voters = <&apps_bcm_voter>;
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};
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nspa_noc: interconnect-nspa-noc {
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compatible = "qcom,sa8775p-nspa-noc";
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#interconnect-cells = <2>;
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qcom,bcm-voters = <&apps_bcm_voter>;
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};
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nspb_noc: interconnect-nspb-noc {
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compatible = "qcom,sa8775p-nspb-noc";
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#interconnect-cells = <2>;
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qcom,bcm-voters = <&apps_bcm_voter>;
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};
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pcie_anoc: interconnect-pcie-anoc {
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compatible = "qcom,sa8775p-pcie-anoc";
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#interconnect-cells = <2>;
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qcom,bcm-voters = <&apps_bcm_voter>;
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};
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system_noc: interconnect-system-noc {
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compatible = "qcom,sa8775p-system-noc";
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#interconnect-cells = <2>;
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qcom,bcm-voters = <&apps_bcm_voter>;
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};
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/* Will be updated by the bootloader. */
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memory@80000000 {
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device_type = "memory";
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reg = <0x0 0x80000000 0x0 0x0>;
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};
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qup_opp_table_100mhz: opp-table-qup100mhz {
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compatible = "operating-points-v2";
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opp-100000000 {
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opp-hz = /bits/ 64 <100000000>;
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required-opps = <&rpmhpd_opp_svs_l1>;
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};
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};
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pmu {
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compatible = "arm,armv8-pmuv3";
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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sail_ss_mem: sail-ss@80000000 {
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reg = <0x0 0x80000000 0x0 0x10000000>;
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no-map;
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};
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hyp_mem: hyp@90000000 {
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reg = <0x0 0x90000000 0x0 0x600000>;
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no-map;
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};
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xbl_boot_mem: xbl-boot@90600000 {
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reg = <0x0 0x90600000 0x0 0x200000>;
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no-map;
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};
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aop_image_mem: aop-image@90800000 {
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reg = <0x0 0x90800000 0x0 0x60000>;
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no-map;
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};
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aop_cmd_db_mem: aop-cmd-db@90860000 {
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compatible = "qcom,cmd-db";
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reg = <0x0 0x90860000 0x0 0x20000>;
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no-map;
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};
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uefi_log: uefi-log@908b0000 {
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reg = <0x0 0x908b0000 0x0 0x10000>;
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no-map;
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};
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reserved_mem: reserved@908f0000 {
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reg = <0x0 0x908f0000 0x0 0xf000>;
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no-map;
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};
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secdata_apss_mem: secdata-apss@908ff000 {
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reg = <0x0 0x908ff000 0x0 0x1000>;
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no-map;
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};
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smem_mem: smem@90900000 {
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compatible = "qcom,smem";
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reg = <0x0 0x90900000 0x0 0x200000>;
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no-map;
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hwlocks = <&tcsr_mutex 3>;
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};
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cpucp_fw_mem: cpucp-fw@90b00000 {
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reg = <0x0 0x90b00000 0x0 0x100000>;
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no-map;
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};
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lpass_machine_learning_mem: lpass-machine-learning@93b00000 {
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reg = <0x0 0x93b00000 0x0 0xf00000>;
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no-map;
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};
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adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@94a00000 {
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reg = <0x0 0x94a00000 0x0 0x800000>;
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no-map;
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};
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pil_camera_mem: pil-camera@95200000 {
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reg = <0x0 0x95200000 0x0 0x500000>;
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no-map;
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};
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pil_adsp_mem: pil-adsp@95c00000 {
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reg = <0x0 0x95c00000 0x0 0x1e00000>;
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no-map;
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};
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pil_gdsp0_mem: pil-gdsp0@97b00000 {
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reg = <0x0 0x97b00000 0x0 0x1e00000>;
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no-map;
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};
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pil_gdsp1_mem: pil-gdsp1@99900000 {
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reg = <0x0 0x99900000 0x0 0x1e00000>;
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no-map;
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};
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pil_cdsp0_mem: pil-cdsp0@9b800000 {
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reg = <0x0 0x9b800000 0x0 0x1e00000>;
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no-map;
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};
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pil_gpu_mem: pil-gpu@9d600000 {
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reg = <0x0 0x9d600000 0x0 0x2000>;
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no-map;
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};
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pil_cdsp1_mem: pil-cdsp1@9d700000 {
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reg = <0x0 0x9d700000 0x0 0x1e00000>;
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no-map;
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};
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pil_cvp_mem: pil-cvp@9f500000 {
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reg = <0x0 0x9f500000 0x0 0x700000>;
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no-map;
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};
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pil_video_mem: pil-video@9fc00000 {
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reg = <0x0 0x9fc00000 0x0 0x700000>;
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no-map;
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};
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hyptz_reserved_mem: hyptz-reserved@beb00000 {
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reg = <0x0 0xbeb00000 0x0 0x11500000>;
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no-map;
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};
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tz_stat_mem: tz-stat@d0000000 {
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reg = <0x0 0xd0000000 0x0 0x100000>;
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no-map;
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};
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tags_mem: tags@d0100000 {
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reg = <0x0 0xd0100000 0x0 0x1200000>;
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no-map;
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};
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qtee_mem: qtee@d1300000 {
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reg = <0x0 0xd1300000 0x0 0x500000>;
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no-map;
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};
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trusted_apps_mem: trusted-apps@d1800000 {
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reg = <0x0 0xd1800000 0x0 0x3900000>;
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no-map;
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};
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};
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soc: soc@0 {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0 0 0 0 0x10 0>;
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gcc: clock-controller@100000 {
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compatible = "qcom,sa8775p-gcc";
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reg = <0x0 0x00100000 0x0 0xc7018>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&sleep_clk>,
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<0>,
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<0>,
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<0>,
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<&usb_0_qmpphy>,
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<&usb_1_qmpphy>,
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<0>,
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<0>,
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<0>,
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<&pcie0_phy>,
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<&pcie1_phy>,
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<0>,
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<0>,
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<0>;
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power-domains = <&rpmhpd SA8775P_CX>;
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};
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ipcc: mailbox@408000 {
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compatible = "qcom,sa8775p-ipcc", "qcom,ipcc";
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reg = <0x0 0x00408000 0x0 0x1000>;
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interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <3>;
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#mbox-cells = <2>;
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};
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qupv3_id_2: geniqup@8c0000 {
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compatible = "qcom,geni-se-qup";
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reg = <0x0 0x008c0000 0x0 0x6000>;
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ranges;
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clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
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clock-names = "m-ahb", "s-ahb";
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iommus = <&apps_smmu 0x5a3 0x0>;
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#address-cells = <2>;
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#size-cells = <2>;
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status = "disabled";
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i2c14: i2c@880000 {
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compatible = "qcom,geni-i2c";
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reg = <0x0 0x880000 0x0 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
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clock-names = "se";
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interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
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&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi14: spi@880000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0x0 0x880000 0x0 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
|
|
clock-names = "se";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c15: i2c@884000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0x0 0x884000 0x0 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
|
|
clock-names = "se";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi15: spi@884000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0x0 0x884000 0x0 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
|
|
clock-names = "se";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c16: i2c@888000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0x0 0x888000 0x0 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
|
|
clock-names = "se";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi16: spi@888000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0x0 0x00888000 0x0 0x4000>;
|
|
interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
|
|
clock-names = "se";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c17: i2c@88c000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0x0 0x88c000 0x0 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
|
|
clock-names = "se";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi17: spi@88c000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0x0 0x88c000 0x0 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
|
|
clock-names = "se";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart17: serial@88c000 {
|
|
compatible = "qcom,geni-uart";
|
|
reg = <0x0 0x0088c000 0x0 0x4000>;
|
|
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
|
|
clock-names = "se";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core", "qup-config";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c18: i2c@890000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0x0 0x00890000 0x0 0x4000>;
|
|
interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
|
|
clock-names = "se";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi18: spi@890000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0x0 0x890000 0x0 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
|
|
clock-names = "se";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c19: i2c@894000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0x0 0x894000 0x0 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
|
|
clock-names = "se";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi19: spi@894000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0x0 0x894000 0x0 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
|
|
clock-names = "se";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c20: i2c@898000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0x0 0x898000 0x0 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
|
|
clock-names = "se";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi20: spi@898000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0x0 0x898000 0x0 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
|
|
clock-names = "se";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
|
|
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
qupv3_id_0: geniqup@9c0000 {
|
|
compatible = "qcom,geni-se-qup";
|
|
reg = <0x0 0x9c0000 0x0 0x6000>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
clock-names = "m-ahb", "s-ahb";
|
|
clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
|
|
iommus = <&apps_smmu 0x403 0x0>;
|
|
status = "disabled";
|
|
|
|
i2c0: i2c@980000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0x0 0x980000 0x0 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
|
|
clock-names = "se";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
|
|
<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi0: spi@980000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0x0 0x980000 0x0 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
|
|
clock-names = "se";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
|
|
<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c1: i2c@984000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0x0 0x984000 0x0 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
|
|
clock-names = "se";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
|
|
<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi1: spi@984000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0x0 0x984000 0x0 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
|
|
clock-names = "se";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
|
|
<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c2: i2c@988000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0x0 0x988000 0x0 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
|
|
clock-names = "se";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
|
|
<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi2: spi@988000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0x0 0x988000 0x0 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
|
|
clock-names = "se";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
|
|
<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c3: i2c@98c000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0x0 0x98c000 0x0 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
|
|
clock-names = "se";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
|
|
<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi3: spi@98c000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0x0 0x98c000 0x0 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
|
|
clock-names = "se";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
|
|
<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c4: i2c@990000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0x0 0x990000 0x0 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
|
|
clock-names = "se";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
|
|
<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi4: spi@990000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0x0 0x990000 0x0 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
|
|
clock-names = "se";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
|
|
<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c5: i2c@994000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0x0 0x994000 0x0 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
|
|
clock-names = "se";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
|
|
<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi5: spi@994000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0x0 0x994000 0x0 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
|
|
clock-names = "se";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
|
|
<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart5: serial@994000 {
|
|
compatible = "qcom,geni-uart";
|
|
reg = <0x0 0x994000 0x0 0x4000>;
|
|
interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
|
|
clock-names = "se";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core", "qup-config";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
qupv3_id_1: geniqup@ac0000 {
|
|
compatible = "qcom,geni-se-qup";
|
|
reg = <0x0 0x00ac0000 0x0 0x6000>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
clock-names = "m-ahb", "s-ahb";
|
|
clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
|
iommus = <&apps_smmu 0x443 0x0>;
|
|
status = "disabled";
|
|
|
|
i2c7: i2c@a80000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0x0 0xa80000 0x0 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
|
|
clock-names = "se";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi7: spi@a80000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0x0 0xa80000 0x0 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
|
|
clock-names = "se";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c8: i2c@a84000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0x0 0xa84000 0x0 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
|
|
clock-names = "se";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi8: spi@a84000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0x0 0xa84000 0x0 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
|
|
clock-names = "se";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c9: i2c@a88000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0x0 0xa88000 0x0 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
|
|
clock-names = "se";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi9: spi@a88000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0x0 0xa88000 0x0 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
|
|
clock-names = "se";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart9: serial@a88000 {
|
|
compatible = "qcom,geni-uart";
|
|
reg = <0x0 0xa88000 0x0 0x4000>;
|
|
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
|
|
clock-names = "se";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core", "qup-config";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c10: i2c@a8c000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0x0 0xa8c000 0x0 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
|
|
clock-names = "se";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi10: spi@a8c000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0x0 0xa8c000 0x0 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
|
|
clock-names = "se";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart10: serial@a8c000 {
|
|
compatible = "qcom,geni-uart";
|
|
reg = <0x0 0x00a8c000 0x0 0x4000>;
|
|
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-names = "se";
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
|
|
interconnect-names = "qup-core", "qup-config";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_1 0
|
|
&clk_virt SLAVE_QUP_CORE_1 0>,
|
|
<&gem_noc MASTER_APPSS_PROC 0
|
|
&config_noc SLAVE_QUP_1 0>;
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
operating-points-v2 = <&qup_opp_table_100mhz>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c11: i2c@a90000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0x0 0xa90000 0x0 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
|
|
clock-names = "se";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi11: spi@a90000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0x0 0xa90000 0x0 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
|
|
clock-names = "se";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c12: i2c@a94000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0x0 0xa94000 0x0 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
|
|
clock-names = "se";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi12: spi@a94000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0x0 0xa94000 0x0 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
|
|
clock-names = "se";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart12: serial@a94000 {
|
|
compatible = "qcom,geni-uart";
|
|
reg = <0x0 0x00a94000 0x0 0x4000>;
|
|
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
|
|
clock-names = "se";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core", "qup-config";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c13: i2c@a98000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0x0 0xa98000 0x0 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
|
|
clock-names = "se";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
|
|
<&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
qupv3_id_3: geniqup@bc0000 {
|
|
compatible = "qcom,geni-se-qup";
|
|
reg = <0x0 0xbc0000 0x0 0x6000>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
clock-names = "m-ahb", "s-ahb";
|
|
clocks = <&gcc GCC_QUPV3_WRAP_3_M_AHB_CLK>,
|
|
<&gcc GCC_QUPV3_WRAP_3_S_AHB_CLK>;
|
|
iommus = <&apps_smmu 0x43 0x0>;
|
|
status = "disabled";
|
|
|
|
i2c21: i2c@b80000 {
|
|
compatible = "qcom,geni-i2c";
|
|
reg = <0x0 0xb80000 0x0 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>;
|
|
clock-names = "se";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>,
|
|
<&aggre1_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi21: spi@b80000 {
|
|
compatible = "qcom,geni-spi";
|
|
reg = <0x0 0xb80000 0x0 0x4000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>;
|
|
clock-names = "se";
|
|
interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS
|
|
&clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>,
|
|
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
|
&config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>,
|
|
<&aggre1_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS
|
|
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
|
interconnect-names = "qup-core",
|
|
"qup-config",
|
|
"qup-memory";
|
|
power-domains = <&rpmhpd SA8775P_CX>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
rng: rng@10d2000 {
|
|
compatible = "qcom,sa8775p-trng", "qcom,trng";
|
|
reg = <0 0x010d2000 0 0x1000>;
|
|
};
|
|
|
|
ufs_mem_hc: ufs@1d84000 {
|
|
compatible = "qcom,sa8775p-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
|
|
reg = <0x0 0x01d84000 0x0 0x3000>;
|
|
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
|
|
phys = <&ufs_mem_phy>;
|
|
phy-names = "ufsphy";
|
|
lanes-per-direction = <2>;
|
|
#reset-cells = <1>;
|
|
resets = <&gcc GCC_UFS_PHY_BCR>;
|
|
reset-names = "rst";
|
|
power-domains = <&gcc UFS_PHY_GDSC>;
|
|
required-opps = <&rpmhpd_opp_nom>;
|
|
iommus = <&apps_smmu 0x100 0x0>;
|
|
dma-coherent;
|
|
clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
|
|
<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
|
|
<&gcc GCC_UFS_PHY_AHB_CLK>,
|
|
<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
|
|
<&rpmhcc RPMH_CXO_CLK>,
|
|
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
|
|
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
|
|
<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
|
|
clock-names = "core_clk",
|
|
"bus_aggr_clk",
|
|
"iface_clk",
|
|
"core_clk_unipro",
|
|
"ref_clk",
|
|
"tx_lane0_sync_clk",
|
|
"rx_lane0_sync_clk",
|
|
"rx_lane1_sync_clk";
|
|
freq-table-hz = <75000000 300000000>,
|
|
<0 0>,
|
|
<0 0>,
|
|
<75000000 300000000>,
|
|
<0 0>,
|
|
<0 0>,
|
|
<0 0>,
|
|
<0 0>;
|
|
qcom,ice = <&ice>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ufs_mem_phy: phy@1d87000 {
|
|
compatible = "qcom,sa8775p-qmp-ufs-phy";
|
|
reg = <0x0 0x01d87000 0x0 0xe10>;
|
|
/*
|
|
* Yes, GCC_EDP_REF_CLKREF_EN is correct in qref. It
|
|
* enables the CXO clock to eDP *and* UFS PHY.
|
|
*/
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
|
<&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
|
|
<&gcc GCC_EDP_REF_CLKREF_EN>;
|
|
clock-names = "ref", "ref_aux", "qref";
|
|
power-domains = <&gcc UFS_PHY_GDSC>;
|
|
resets = <&ufs_mem_hc 0>;
|
|
reset-names = "ufsphy";
|
|
#phy-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ice: crypto@1d88000 {
|
|
compatible = "qcom,sa8775p-inline-crypto-engine",
|
|
"qcom,inline-crypto-engine";
|
|
reg = <0x0 0x01d88000 0x0 0x8000>;
|
|
clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
|
|
};
|
|
|
|
usb_0_hsphy: phy@88e4000 {
|
|
compatible = "qcom,sa8775p-usb-hs-phy",
|
|
"qcom,usb-snps-hs-5nm-phy";
|
|
reg = <0 0x088e4000 0 0x120>;
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
|
clock-names = "ref";
|
|
resets = <&gcc GCC_USB2_PHY_PRIM_BCR>;
|
|
|
|
#phy-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
usb_0_qmpphy: phy@88e8000 {
|
|
compatible = "qcom,sa8775p-qmp-usb3-uni-phy";
|
|
reg = <0 0x088e8000 0 0x2000>;
|
|
|
|
clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
|
|
<&gcc GCC_USB_CLKREF_EN>,
|
|
<&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
|
|
<&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
|
|
clock-names = "aux", "ref", "com_aux", "pipe";
|
|
|
|
resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
|
|
<&gcc GCC_USB3PHY_PHY_PRIM_BCR>;
|
|
reset-names = "phy", "phy_phy";
|
|
|
|
power-domains = <&gcc USB30_PRIM_GDSC>;
|
|
|
|
#clock-cells = <0>;
|
|
clock-output-names = "usb3_prim_phy_pipe_clk_src";
|
|
|
|
#phy-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
usb_0: usb@a6f8800 {
|
|
compatible = "qcom,sa8775p-dwc3", "qcom,dwc3";
|
|
reg = <0 0x0a6f8800 0 0x400>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
|
|
clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
|
|
<&gcc GCC_USB30_PRIM_MASTER_CLK>,
|
|
<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
|
|
<&gcc GCC_USB30_PRIM_SLEEP_CLK>,
|
|
<&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
|
|
clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi";
|
|
|
|
assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
|
|
<&gcc GCC_USB30_PRIM_MASTER_CLK>;
|
|
assigned-clock-rates = <19200000>, <200000000>;
|
|
|
|
interrupts-extended = <&intc GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>,
|
|
<&pdc 14 IRQ_TYPE_EDGE_BOTH>,
|
|
<&pdc 15 IRQ_TYPE_EDGE_BOTH>,
|
|
<&pdc 12 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "pwr_event",
|
|
"dp_hs_phy_irq",
|
|
"dm_hs_phy_irq",
|
|
"ss_phy_irq";
|
|
|
|
power-domains = <&gcc USB30_PRIM_GDSC>;
|
|
required-opps = <&rpmhpd_opp_nom>;
|
|
|
|
resets = <&gcc GCC_USB30_PRIM_BCR>;
|
|
|
|
interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
|
|
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
|
|
interconnect-names = "usb-ddr", "apps-usb";
|
|
|
|
wakeup-source;
|
|
|
|
status = "disabled";
|
|
|
|
usb_0_dwc3: usb@a600000 {
|
|
compatible = "snps,dwc3";
|
|
reg = <0 0x0a600000 0 0xe000>;
|
|
interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>;
|
|
iommus = <&apps_smmu 0x080 0x0>;
|
|
phys = <&usb_0_hsphy>, <&usb_0_qmpphy>;
|
|
phy-names = "usb2-phy", "usb3-phy";
|
|
};
|
|
};
|
|
|
|
usb_1_hsphy: phy@88e6000 {
|
|
compatible = "qcom,sa8775p-usb-hs-phy",
|
|
"qcom,usb-snps-hs-5nm-phy";
|
|
reg = <0 0x088e6000 0 0x120>;
|
|
clocks = <&gcc GCC_USB_CLKREF_EN>;
|
|
clock-names = "ref";
|
|
resets = <&gcc GCC_USB2_PHY_SEC_BCR>;
|
|
|
|
#phy-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
usb_1_qmpphy: phy@88ea000 {
|
|
compatible = "qcom,sa8775p-qmp-usb3-uni-phy";
|
|
reg = <0 0x088ea000 0 0x2000>;
|
|
|
|
clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
|
|
<&gcc GCC_USB_CLKREF_EN>,
|
|
<&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
|
|
<&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
|
|
clock-names = "aux", "ref", "com_aux", "pipe";
|
|
|
|
resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
|
|
<&gcc GCC_USB3PHY_PHY_SEC_BCR>;
|
|
reset-names = "phy", "phy_phy";
|
|
|
|
power-domains = <&gcc USB30_SEC_GDSC>;
|
|
|
|
#clock-cells = <0>;
|
|
clock-output-names = "usb3_sec_phy_pipe_clk_src";
|
|
|
|
#phy-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
usb_1: usb@a8f8800 {
|
|
compatible = "qcom,sa8775p-dwc3", "qcom,dwc3";
|
|
reg = <0 0x0a8f8800 0 0x400>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
|
|
clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
|
|
<&gcc GCC_USB30_SEC_MASTER_CLK>,
|
|
<&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
|
|
<&gcc GCC_USB30_SEC_SLEEP_CLK>,
|
|
<&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>;
|
|
clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi";
|
|
|
|
assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
|
|
<&gcc GCC_USB30_SEC_MASTER_CLK>;
|
|
assigned-clock-rates = <19200000>, <200000000>;
|
|
|
|
interrupts-extended = <&intc GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
|
|
<&pdc 8 IRQ_TYPE_EDGE_BOTH>,
|
|
<&pdc 7 IRQ_TYPE_EDGE_BOTH>,
|
|
<&pdc 13 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "pwr_event",
|
|
"dp_hs_phy_irq",
|
|
"dm_hs_phy_irq",
|
|
"ss_phy_irq";
|
|
|
|
power-domains = <&gcc USB30_SEC_GDSC>;
|
|
required-opps = <&rpmhpd_opp_nom>;
|
|
|
|
resets = <&gcc GCC_USB30_SEC_BCR>;
|
|
|
|
interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>,
|
|
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
|
|
interconnect-names = "usb-ddr", "apps-usb";
|
|
|
|
wakeup-source;
|
|
|
|
status = "disabled";
|
|
|
|
usb_1_dwc3: usb@a800000 {
|
|
compatible = "snps,dwc3";
|
|
reg = <0 0x0a800000 0 0xe000>;
|
|
interrupts = <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>;
|
|
iommus = <&apps_smmu 0x0a0 0x0>;
|
|
phys = <&usb_1_hsphy>, <&usb_1_qmpphy>;
|
|
phy-names = "usb2-phy", "usb3-phy";
|
|
};
|
|
};
|
|
|
|
usb_2_hsphy: phy@88e7000 {
|
|
compatible = "qcom,sa8775p-usb-hs-phy",
|
|
"qcom,usb-snps-hs-5nm-phy";
|
|
reg = <0 0x088e7000 0 0x120>;
|
|
clocks = <&gcc GCC_USB_CLKREF_EN>;
|
|
clock-names = "ref";
|
|
resets = <&gcc GCC_USB3_PHY_TERT_BCR>;
|
|
|
|
#phy-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
usb_2: usb@a4f8800 {
|
|
compatible = "qcom,sa8775p-dwc3", "qcom,dwc3";
|
|
reg = <0 0x0a4f8800 0 0x400>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
|
|
clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>,
|
|
<&gcc GCC_USB20_MASTER_CLK>,
|
|
<&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>,
|
|
<&gcc GCC_USB20_SLEEP_CLK>,
|
|
<&gcc GCC_USB20_MOCK_UTMI_CLK>;
|
|
clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi";
|
|
|
|
assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
|
|
<&gcc GCC_USB20_MASTER_CLK>;
|
|
assigned-clock-rates = <19200000>, <200000000>;
|
|
|
|
interrupts-extended = <&intc GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
|
|
<&pdc 10 IRQ_TYPE_EDGE_BOTH>,
|
|
<&pdc 9 IRQ_TYPE_EDGE_BOTH>;
|
|
interrupt-names = "pwr_event",
|
|
"dp_hs_phy_irq",
|
|
"dm_hs_phy_irq";
|
|
|
|
power-domains = <&gcc USB20_PRIM_GDSC>;
|
|
required-opps = <&rpmhpd_opp_nom>;
|
|
|
|
resets = <&gcc GCC_USB20_PRIM_BCR>;
|
|
|
|
interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>,
|
|
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB2 0>;
|
|
interconnect-names = "usb-ddr", "apps-usb";
|
|
|
|
wakeup-source;
|
|
|
|
status = "disabled";
|
|
|
|
usb_2_dwc3: usb@a400000 {
|
|
compatible = "snps,dwc3";
|
|
reg = <0 0x0a400000 0 0xe000>;
|
|
interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>;
|
|
iommus = <&apps_smmu 0x020 0x0>;
|
|
phys = <&usb_2_hsphy>;
|
|
phy-names = "usb2-phy";
|
|
};
|
|
};
|
|
|
|
tcsr_mutex: hwlock@1f40000 {
|
|
compatible = "qcom,tcsr-mutex";
|
|
reg = <0x0 0x01f40000 0x0 0x20000>;
|
|
#hwlock-cells = <1>;
|
|
};
|
|
|
|
gpucc: clock-controller@3d90000 {
|
|
compatible = "qcom,sa8775p-gpucc";
|
|
reg = <0x0 0x03d90000 0x0 0xa000>;
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
|
<&gcc GCC_GPU_GPLL0_CLK_SRC>,
|
|
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
|
|
clock-names = "bi_tcxo",
|
|
"gcc_gpu_gpll0_clk_src",
|
|
"gcc_gpu_gpll0_div_clk_src";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
#power-domain-cells = <1>;
|
|
};
|
|
|
|
adreno_smmu: iommu@3da0000 {
|
|
compatible = "qcom,sa8775p-smmu-500", "qcom,adreno-smmu",
|
|
"qcom,smmu-500", "arm,mmu-500";
|
|
reg = <0x0 0x03da0000 0x0 0x20000>;
|
|
#iommu-cells = <2>;
|
|
#global-interrupts = <2>;
|
|
dma-coherent;
|
|
power-domains = <&gpucc GPU_CC_CX_GDSC>;
|
|
clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
|
|
<&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
|
|
<&gpucc GPU_CC_AHB_CLK>,
|
|
<&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
|
|
<&gpucc GPU_CC_CX_GMU_CLK>,
|
|
<&gpucc GPU_CC_HUB_CX_INT_CLK>,
|
|
<&gpucc GPU_CC_HUB_AON_CLK>;
|
|
clock-names = "gcc_gpu_memnoc_gfx_clk",
|
|
"gcc_gpu_snoc_dvm_gfx_clk",
|
|
"gpu_cc_ahb_clk",
|
|
"gpu_cc_hlos1_vote_gpu_smmu_clk",
|
|
"gpu_cc_cx_gmu_clk",
|
|
"gpu_cc_hub_cx_int_clk",
|
|
"gpu_cc_hub_aon_clk";
|
|
interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
serdes0: phy@8901000 {
|
|
compatible = "qcom,sa8775p-dwmac-sgmii-phy";
|
|
reg = <0x0 0x08901000 0x0 0xe10>;
|
|
clocks = <&gcc GCC_SGMI_CLKREF_EN>;
|
|
clock-names = "sgmi_ref";
|
|
#phy-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
serdes1: phy@8902000 {
|
|
compatible = "qcom,sa8775p-dwmac-sgmii-phy";
|
|
reg = <0x0 0x08902000 0x0 0xe10>;
|
|
clocks = <&gcc GCC_SGMI_CLKREF_EN>;
|
|
clock-names = "sgmi_ref";
|
|
#phy-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pdc: interrupt-controller@b220000 {
|
|
compatible = "qcom,sa8775p-pdc", "qcom,pdc";
|
|
reg = <0x0 0x0b220000 0x0 0x30000>,
|
|
<0x0 0x17c000f0 0x0 0x64>;
|
|
qcom,pdc-ranges = <0 480 40>,
|
|
<40 140 14>,
|
|
<54 263 1>,
|
|
<55 306 4>,
|
|
<59 312 3>,
|
|
<62 374 2>,
|
|
<64 434 2>,
|
|
<66 438 2>,
|
|
<70 520 1>,
|
|
<73 523 1>,
|
|
<118 568 6>,
|
|
<124 609 3>,
|
|
<159 638 1>,
|
|
<160 720 3>,
|
|
<169 728 30>,
|
|
<199 416 2>,
|
|
<201 449 1>,
|
|
<202 89 1>,
|
|
<203 451 1>,
|
|
<204 462 1>,
|
|
<205 264 1>,
|
|
<206 579 1>,
|
|
<207 653 1>,
|
|
<208 656 1>,
|
|
<209 659 1>,
|
|
<210 122 1>,
|
|
<211 699 1>,
|
|
<212 705 1>,
|
|
<213 450 1>,
|
|
<214 643 2>,
|
|
<216 646 5>,
|
|
<221 390 5>,
|
|
<226 700 2>,
|
|
<228 440 1>,
|
|
<229 663 1>,
|
|
<230 524 2>,
|
|
<232 612 3>,
|
|
<235 723 5>;
|
|
#interrupt-cells = <2>;
|
|
interrupt-parent = <&intc>;
|
|
interrupt-controller;
|
|
};
|
|
|
|
tsens2: thermal-sensor@c251000 {
|
|
compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2";
|
|
reg = <0x0 0x0c251000 0x0 0x1ff>,
|
|
<0x0 0x0c224000 0x0 0x8>;
|
|
interrupts = <GIC_SPI 572 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 609 IRQ_TYPE_LEVEL_HIGH>;
|
|
#qcom,sensors = <13>;
|
|
interrupt-names = "uplow", "critical";
|
|
#thermal-sensor-cells = <1>;
|
|
};
|
|
|
|
tsens3: thermal-sensor@c252000 {
|
|
compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2";
|
|
reg = <0x0 0x0c252000 0x0 0x1ff>,
|
|
<0x0 0x0c225000 0x0 0x8>;
|
|
interrupts = <GIC_SPI 573 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>;
|
|
#qcom,sensors = <13>;
|
|
interrupt-names = "uplow", "critical";
|
|
#thermal-sensor-cells = <1>;
|
|
};
|
|
|
|
tsens0: thermal-sensor@c263000 {
|
|
compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2";
|
|
reg = <0x0 0x0c263000 0x0 0x1ff>,
|
|
<0x0 0x0c222000 0x0 0x8>;
|
|
interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
|
|
#qcom,sensors = <12>;
|
|
interrupt-names = "uplow", "critical";
|
|
#thermal-sensor-cells = <1>;
|
|
};
|
|
|
|
tsens1: thermal-sensor@c265000 {
|
|
compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2";
|
|
reg = <0x0 0x0c265000 0x0 0x1ff>,
|
|
<0x0 0x0c223000 0x0 0x8>;
|
|
interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
|
|
#qcom,sensors = <12>;
|
|
interrupt-names = "uplow", "critical";
|
|
#thermal-sensor-cells = <1>;
|
|
};
|
|
|
|
aoss_qmp: power-management@c300000 {
|
|
compatible = "qcom,sa8775p-aoss-qmp", "qcom,aoss-qmp";
|
|
reg = <0x0 0x0c300000 0x0 0x400>;
|
|
interrupts-extended = <&ipcc IPCC_CLIENT_AOP
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP
|
|
IRQ_TYPE_EDGE_RISING>;
|
|
mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
sram@c3f0000 {
|
|
compatible = "qcom,rpmh-stats";
|
|
reg = <0x0 0x0c3f0000 0x0 0x400>;
|
|
};
|
|
|
|
spmi_bus: spmi@c440000 {
|
|
compatible = "qcom,spmi-pmic-arb";
|
|
reg = <0x0 0x0c440000 0x0 0x1100>,
|
|
<0x0 0x0c600000 0x0 0x2000000>,
|
|
<0x0 0x0e600000 0x0 0x100000>,
|
|
<0x0 0x0e700000 0x0 0xa0000>,
|
|
<0x0 0x0c40a000 0x0 0x26000>;
|
|
reg-names = "core",
|
|
"chnls",
|
|
"obsrvr",
|
|
"intr",
|
|
"cnfg";
|
|
qcom,channel = <0>;
|
|
qcom,ee = <0>;
|
|
interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "periph_irq";
|
|
interrupt-controller;
|
|
#interrupt-cells = <4>;
|
|
#address-cells = <2>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
tlmm: pinctrl@f000000 {
|
|
compatible = "qcom,sa8775p-tlmm";
|
|
reg = <0x0 0x0f000000 0x0 0x1000000>;
|
|
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
gpio-ranges = <&tlmm 0 0 149>;
|
|
wakeup-parent = <&pdc>;
|
|
};
|
|
|
|
apps_smmu: iommu@15000000 {
|
|
compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500";
|
|
reg = <0x0 0x15000000 0x0 0x100000>;
|
|
#iommu-cells = <2>;
|
|
#global-interrupts = <2>;
|
|
|
|
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
pcie_smmu: iommu@15200000 {
|
|
compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500";
|
|
reg = <0x0 0x15200000 0x0 0x80000>;
|
|
#iommu-cells = <2>;
|
|
#global-interrupts = <2>;
|
|
|
|
interrupts = <GIC_SPI 920 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 921 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 925 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 926 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 927 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 928 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 950 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 951 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 952 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 953 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 954 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 955 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 956 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 957 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 958 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 885 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 886 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 888 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 843 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 845 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 847 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 814 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 854 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 855 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
intc: interrupt-controller@17a00000 {
|
|
compatible = "arm,gic-v3";
|
|
reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
|
|
<0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
|
#redistributor-regions = <1>;
|
|
redistributor-stride = <0x0 0x20000>;
|
|
};
|
|
|
|
watchdog@17c10000 {
|
|
compatible = "qcom,apss-wdt-sa8775p", "qcom,kpss-wdt";
|
|
reg = <0x0 0x17c10000 0x0 0x1000>;
|
|
clocks = <&sleep_clk>;
|
|
interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
|
|
};
|
|
|
|
memtimer: timer@17c20000 {
|
|
compatible = "arm,armv7-timer-mem";
|
|
reg = <0x0 0x17c20000 0x0 0x1000>;
|
|
ranges = <0x0 0x0 0x0 0x20000000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
frame@17c21000 {
|
|
reg = <0x17c21000 0x1000>,
|
|
<0x17c22000 0x1000>;
|
|
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
|
|
frame-number = <0>;
|
|
};
|
|
|
|
frame@17c23000 {
|
|
reg = <0x17c23000 0x1000>;
|
|
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
|
frame-number = <1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17c25000 {
|
|
reg = <0x17c25000 0x1000>;
|
|
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
|
frame-number = <2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17c27000 {
|
|
reg = <0x17c27000 0x1000>;
|
|
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
|
frame-number = <3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17c29000 {
|
|
reg = <0x17c29000 0x1000>;
|
|
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
|
frame-number = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17c2b000 {
|
|
reg = <0x17c2b000 0x1000>;
|
|
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
|
frame-number = <5>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17c2d000 {
|
|
reg = <0x17c2d000 0x1000>;
|
|
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
|
frame-number = <6>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
apps_rsc: rsc@18200000 {
|
|
compatible = "qcom,rpmh-rsc";
|
|
reg = <0x0 0x18200000 0x0 0x10000>,
|
|
<0x0 0x18210000 0x0 0x10000>,
|
|
<0x0 0x18220000 0x0 0x10000>;
|
|
reg-names = "drv-0", "drv-1", "drv-2";
|
|
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
|
qcom,tcs-offset = <0xd00>;
|
|
qcom,drv-id = <2>;
|
|
qcom,tcs-config = <ACTIVE_TCS 2>,
|
|
<SLEEP_TCS 3>,
|
|
<WAKE_TCS 3>,
|
|
<CONTROL_TCS 0>;
|
|
label = "apps_rsc";
|
|
|
|
apps_bcm_voter: bcm-voter {
|
|
compatible = "qcom,bcm-voter";
|
|
};
|
|
|
|
rpmhcc: clock-controller {
|
|
compatible = "qcom,sa8775p-rpmh-clk";
|
|
#clock-cells = <1>;
|
|
clock-names = "xo";
|
|
clocks = <&xo_board_clk>;
|
|
};
|
|
|
|
rpmhpd: power-controller {
|
|
compatible = "qcom,sa8775p-rpmhpd";
|
|
#power-domain-cells = <1>;
|
|
operating-points-v2 = <&rpmhpd_opp_table>;
|
|
|
|
rpmhpd_opp_table: opp-table {
|
|
compatible = "operating-points-v2";
|
|
|
|
rpmhpd_opp_ret: opp-0 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
|
|
};
|
|
|
|
rpmhpd_opp_min_svs: opp-1 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
|
|
};
|
|
|
|
rpmhpd_opp_low_svs: opp2 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
|
};
|
|
|
|
rpmhpd_opp_svs: opp3 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
|
|
};
|
|
|
|
rpmhpd_opp_svs_l1: opp-4 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
|
};
|
|
|
|
rpmhpd_opp_nom: opp-5 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
|
|
};
|
|
|
|
rpmhpd_opp_nom_l1: opp-6 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
|
|
};
|
|
|
|
rpmhpd_opp_nom_l2: opp-7 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
|
|
};
|
|
|
|
rpmhpd_opp_turbo: opp-8 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
|
|
};
|
|
|
|
rpmhpd_opp_turbo_l1: opp-9 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
cpufreq_hw: cpufreq@18591000 {
|
|
compatible = "qcom,sa8775p-cpufreq-epss",
|
|
"qcom,cpufreq-epss";
|
|
reg = <0x0 0x18591000 0x0 0x1000>,
|
|
<0x0 0x18593000 0x0 0x1000>;
|
|
reg-names = "freq-domain0", "freq-domain1";
|
|
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
|
|
clock-names = "xo", "alternate";
|
|
|
|
#freq-domain-cells = <1>;
|
|
};
|
|
|
|
ethernet1: ethernet@23000000 {
|
|
compatible = "qcom,sa8775p-ethqos";
|
|
reg = <0x0 0x23000000 0x0 0x10000>,
|
|
<0x0 0x23016000 0x0 0x100>;
|
|
reg-names = "stmmaceth", "rgmii";
|
|
|
|
interrupts = <GIC_SPI 929 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "macirq";
|
|
|
|
clocks = <&gcc GCC_EMAC1_AXI_CLK>,
|
|
<&gcc GCC_EMAC1_SLV_AHB_CLK>,
|
|
<&gcc GCC_EMAC1_PTP_CLK>,
|
|
<&gcc GCC_EMAC1_PHY_AUX_CLK>;
|
|
clock-names = "stmmaceth",
|
|
"pclk",
|
|
"ptp_ref",
|
|
"phyaux";
|
|
|
|
power-domains = <&gcc EMAC1_GDSC>;
|
|
|
|
phys = <&serdes1>;
|
|
phy-names = "serdes";
|
|
|
|
iommus = <&apps_smmu 0x140 0xf>;
|
|
|
|
snps,tso;
|
|
snps,pbl = <32>;
|
|
rx-fifo-depth = <16384>;
|
|
tx-fifo-depth = <16384>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
ethernet0: ethernet@23040000 {
|
|
compatible = "qcom,sa8775p-ethqos";
|
|
reg = <0x0 0x23040000 0x0 0x10000>,
|
|
<0x0 0x23056000 0x0 0x100>;
|
|
reg-names = "stmmaceth", "rgmii";
|
|
|
|
interrupts = <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "macirq";
|
|
|
|
clocks = <&gcc GCC_EMAC0_AXI_CLK>,
|
|
<&gcc GCC_EMAC0_SLV_AHB_CLK>,
|
|
<&gcc GCC_EMAC0_PTP_CLK>,
|
|
<&gcc GCC_EMAC0_PHY_AUX_CLK>;
|
|
clock-names = "stmmaceth",
|
|
"pclk",
|
|
"ptp_ref",
|
|
"phyaux";
|
|
|
|
power-domains = <&gcc EMAC0_GDSC>;
|
|
|
|
phys = <&serdes0>;
|
|
phy-names = "serdes";
|
|
|
|
iommus = <&apps_smmu 0x120 0xf>;
|
|
|
|
snps,tso;
|
|
snps,pbl = <32>;
|
|
rx-fifo-depth = <16384>;
|
|
tx-fifo-depth = <16384>;
|
|
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
thermal-zones {
|
|
aoss-0-thermal {
|
|
polling-delay-passive = <0>;
|
|
polling-delay = <0>;
|
|
|
|
thermal-sensors = <&tsens0 0>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-0-0-0-thermal {
|
|
polling-delay-passive = <10>;
|
|
polling-delay = <0>;
|
|
|
|
thermal-sensors = <&tsens0 1>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-0-1-0-thermal {
|
|
polling-delay-passive = <10>;
|
|
polling-delay = <0>;
|
|
|
|
thermal-sensors = <&tsens0 2>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-0-2-0-thermal {
|
|
polling-delay-passive = <10>;
|
|
polling-delay = <0>;
|
|
|
|
thermal-sensors = <&tsens0 3>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-0-3-0-thermal {
|
|
polling-delay-passive = <10>;
|
|
polling-delay = <0>;
|
|
|
|
thermal-sensors = <&tsens0 4>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
gpuss-0-thermal {
|
|
polling-delay-passive = <10>;
|
|
polling-delay = <0>;
|
|
|
|
thermal-sensors = <&tsens0 5>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
gpuss-1-thermal {
|
|
polling-delay-passive = <10>;
|
|
polling-delay = <0>;
|
|
|
|
thermal-sensors = <&tsens0 6>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
gpuss-2-thermal {
|
|
polling-delay-passive = <10>;
|
|
polling-delay = <0>;
|
|
|
|
thermal-sensors = <&tsens0 7>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
audio-thermal {
|
|
polling-delay-passive = <0>;
|
|
polling-delay = <0>;
|
|
|
|
thermal-sensors = <&tsens0 8>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
camss-0-thermal {
|
|
polling-delay-passive = <0>;
|
|
polling-delay = <0>;
|
|
|
|
thermal-sensors = <&tsens0 9>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
pcie-0-thermal {
|
|
polling-delay-passive = <0>;
|
|
polling-delay = <0>;
|
|
|
|
thermal-sensors = <&tsens0 10>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpuss-0-0-thermal {
|
|
polling-delay-passive = <0>;
|
|
polling-delay = <0>;
|
|
|
|
thermal-sensors = <&tsens0 11>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
aoss-1-thermal {
|
|
polling-delay-passive = <0>;
|
|
polling-delay = <0>;
|
|
|
|
thermal-sensors = <&tsens1 0>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-0-0-1-thermal {
|
|
polling-delay-passive = <10>;
|
|
polling-delay = <0>;
|
|
|
|
thermal-sensors = <&tsens1 1>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-0-1-1-thermal {
|
|
polling-delay-passive = <10>;
|
|
polling-delay = <0>;
|
|
|
|
thermal-sensors = <&tsens1 2>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-0-2-1-thermal {
|
|
polling-delay-passive = <10>;
|
|
polling-delay = <0>;
|
|
|
|
thermal-sensors = <&tsens1 3>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-0-3-1-thermal {
|
|
polling-delay-passive = <10>;
|
|
polling-delay = <0>;
|
|
|
|
thermal-sensors = <&tsens1 4>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
gpuss-3-thermal {
|
|
polling-delay-passive = <10>;
|
|
polling-delay = <0>;
|
|
|
|
thermal-sensors = <&tsens1 5>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
gpuss-4-thermal {
|
|
polling-delay-passive = <10>;
|
|
polling-delay = <0>;
|
|
|
|
thermal-sensors = <&tsens1 6>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
gpuss-5-thermal {
|
|
polling-delay-passive = <10>;
|
|
polling-delay = <0>;
|
|
|
|
thermal-sensors = <&tsens1 7>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
video-thermal {
|
|
polling-delay-passive = <0>;
|
|
polling-delay = <0>;
|
|
|
|
thermal-sensors = <&tsens1 8>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
camss-1-thermal {
|
|
polling-delay-passive = <0>;
|
|
polling-delay = <0>;
|
|
|
|
thermal-sensors = <&tsens1 9>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
pcie-1-thermal {
|
|
polling-delay-passive = <0>;
|
|
polling-delay = <0>;
|
|
|
|
thermal-sensors = <&tsens1 10>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpuss-0-1-thermal {
|
|
polling-delay-passive = <0>;
|
|
polling-delay = <0>;
|
|
|
|
thermal-sensors = <&tsens1 11>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
aoss-2-thermal {
|
|
polling-delay-passive = <0>;
|
|
polling-delay = <0>;
|
|
|
|
thermal-sensors = <&tsens2 0>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-1-0-0-thermal {
|
|
polling-delay-passive = <10>;
|
|
polling-delay = <0>;
|
|
|
|
thermal-sensors = <&tsens2 1>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-1-1-0-thermal {
|
|
polling-delay-passive = <10>;
|
|
polling-delay = <0>;
|
|
|
|
thermal-sensors = <&tsens2 2>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-1-2-0-thermal {
|
|
polling-delay-passive = <10>;
|
|
polling-delay = <0>;
|
|
|
|
thermal-sensors = <&tsens2 3>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-1-3-0-thermal {
|
|
polling-delay-passive = <10>;
|
|
polling-delay = <0>;
|
|
|
|
thermal-sensors = <&tsens2 4>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
nsp-0-0-0-thermal {
|
|
polling-delay-passive = <10>;
|
|
polling-delay = <0>;
|
|
|
|
thermal-sensors = <&tsens2 5>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
nsp-0-1-0-thermal {
|
|
polling-delay-passive = <10>;
|
|
polling-delay = <0>;
|
|
|
|
thermal-sensors = <&tsens2 6>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
nsp-0-2-0-thermal {
|
|
polling-delay-passive = <10>;
|
|
polling-delay = <0>;
|
|
|
|
thermal-sensors = <&tsens2 7>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
nsp-1-0-0-thermal {
|
|
polling-delay-passive = <10>;
|
|
polling-delay = <0>;
|
|
|
|
thermal-sensors = <&tsens2 8>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
nsp-1-1-0-thermal {
|
|
polling-delay-passive = <10>;
|
|
polling-delay = <0>;
|
|
|
|
thermal-sensors = <&tsens2 9>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
nsp-1-2-0-thermal {
|
|
polling-delay-passive = <10>;
|
|
polling-delay = <0>;
|
|
|
|
thermal-sensors = <&tsens2 10>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
ddrss-0-thermal {
|
|
polling-delay-passive = <0>;
|
|
polling-delay = <0>;
|
|
|
|
thermal-sensors = <&tsens2 11>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpuss-1-0-thermal {
|
|
polling-delay-passive = <0>;
|
|
polling-delay = <0>;
|
|
|
|
thermal-sensors = <&tsens2 12>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
aoss-3-thermal {
|
|
polling-delay-passive = <0>;
|
|
polling-delay = <0>;
|
|
|
|
thermal-sensors = <&tsens3 0>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-1-0-1-thermal {
|
|
polling-delay-passive = <10>;
|
|
polling-delay = <0>;
|
|
|
|
thermal-sensors = <&tsens3 1>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-1-1-1-thermal {
|
|
polling-delay-passive = <10>;
|
|
polling-delay = <0>;
|
|
|
|
thermal-sensors = <&tsens3 2>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-1-2-1-thermal {
|
|
polling-delay-passive = <10>;
|
|
polling-delay = <0>;
|
|
|
|
thermal-sensors = <&tsens3 3>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpu-1-3-1-thermal {
|
|
polling-delay-passive = <10>;
|
|
polling-delay = <0>;
|
|
|
|
thermal-sensors = <&tsens3 4>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
nsp-0-0-1-thermal {
|
|
polling-delay-passive = <10>;
|
|
polling-delay = <0>;
|
|
|
|
thermal-sensors = <&tsens3 5>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
nsp-0-1-1-thermal {
|
|
polling-delay-passive = <10>;
|
|
polling-delay = <0>;
|
|
|
|
thermal-sensors = <&tsens3 6>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
nsp-0-2-1-thermal {
|
|
polling-delay-passive = <10>;
|
|
polling-delay = <0>;
|
|
|
|
thermal-sensors = <&tsens3 7>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
nsp-1-0-1-thermal {
|
|
polling-delay-passive = <10>;
|
|
polling-delay = <0>;
|
|
|
|
thermal-sensors = <&tsens3 8>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
nsp-1-1-1-thermal {
|
|
polling-delay-passive = <10>;
|
|
polling-delay = <0>;
|
|
|
|
thermal-sensors = <&tsens3 9>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
nsp-1-2-1-thermal {
|
|
polling-delay-passive = <10>;
|
|
polling-delay = <0>;
|
|
|
|
thermal-sensors = <&tsens3 10>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
ddrss-1-thermal {
|
|
polling-delay-passive = <0>;
|
|
polling-delay = <0>;
|
|
|
|
thermal-sensors = <&tsens3 11>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
|
|
cpuss-1-1-thermal {
|
|
polling-delay-passive = <0>;
|
|
polling-delay = <0>;
|
|
|
|
thermal-sensors = <&tsens3 12>;
|
|
|
|
trips {
|
|
trip-point0 {
|
|
temperature = <105000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
|
|
trip-point1 {
|
|
temperature = <115000>;
|
|
hysteresis = <5000>;
|
|
type = "passive";
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
arch_timer: timer {
|
|
compatible = "arm,armv8-timer";
|
|
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
|
|
};
|
|
|
|
pcie0: pcie@1c00000 {
|
|
compatible = "qcom,pcie-sa8775p";
|
|
reg = <0x0 0x01c00000 0x0 0x3000>,
|
|
<0x0 0x40000000 0x0 0xf20>,
|
|
<0x0 0x40000f20 0x0 0xa8>,
|
|
<0x0 0x40001000 0x0 0x4000>,
|
|
<0x0 0x40100000 0x0 0x100000>,
|
|
<0x0 0x01c03000 0x0 0x1000>;
|
|
reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
|
|
device_type = "pci";
|
|
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
|
|
<0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
|
|
bus-range = <0x00 0xff>;
|
|
|
|
dma-coherent;
|
|
|
|
linux,pci-domain = <0>;
|
|
num-lanes = <2>;
|
|
|
|
interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "msi0", "msi1", "msi2", "msi3",
|
|
"msi4", "msi5", "msi6", "msi7";
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0 0 0x7>;
|
|
interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
|
|
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
|
|
<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
|
|
<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
|
|
<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>;
|
|
|
|
clock-names = "aux",
|
|
"cfg",
|
|
"bus_master",
|
|
"bus_slave",
|
|
"slave_q2a";
|
|
|
|
assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>;
|
|
assigned-clock-rates = <19200000>;
|
|
|
|
interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>,
|
|
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>;
|
|
interconnect-names = "pcie-mem", "cpu-pcie";
|
|
|
|
iommu-map = <0x0 &pcie_smmu 0x0000 0x1>,
|
|
<0x100 &pcie_smmu 0x0001 0x1>;
|
|
|
|
resets = <&gcc GCC_PCIE_0_BCR>;
|
|
reset-names = "pci";
|
|
power-domains = <&gcc PCIE_0_GDSC>;
|
|
|
|
phys = <&pcie0_phy>;
|
|
phy-names = "pciephy";
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
pcie0_phy: phy@1c04000 {
|
|
compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy";
|
|
reg = <0x0 0x1c04000 0x0 0x2000>;
|
|
|
|
clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
|
|
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
|
|
<&gcc GCC_PCIE_CLKREF_EN>,
|
|
<&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
|
|
<&gcc GCC_PCIE_0_PIPE_CLK>,
|
|
<&gcc GCC_PCIE_0_PIPEDIV2_CLK>,
|
|
<&gcc GCC_PCIE_0_PHY_AUX_CLK>;
|
|
|
|
clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe",
|
|
"pipediv2", "phy_aux";
|
|
|
|
assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
|
|
assigned-clock-rates = <100000000>;
|
|
|
|
resets = <&gcc GCC_PCIE_0_PHY_BCR>;
|
|
reset-names = "phy";
|
|
|
|
#clock-cells = <0>;
|
|
clock-output-names = "pcie_0_pipe_clk";
|
|
|
|
#phy-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
pcie1: pcie@1c10000 {
|
|
compatible = "qcom,pcie-sa8775p";
|
|
reg = <0x0 0x01c10000 0x0 0x3000>,
|
|
<0x0 0x60000000 0x0 0xf20>,
|
|
<0x0 0x60000f20 0x0 0xa8>,
|
|
<0x0 0x60001000 0x0 0x4000>,
|
|
<0x0 0x60100000 0x0 0x100000>,
|
|
<0x0 0x01c13000 0x0 0x1000>;
|
|
reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
|
|
device_type = "pci";
|
|
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
|
|
<0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x1fd00000>;
|
|
bus-range = <0x00 0xff>;
|
|
|
|
dma-coherent;
|
|
|
|
linux,pci-domain = <1>;
|
|
num-lanes = <4>;
|
|
|
|
interrupts = <GIC_SPI 519 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "msi0", "msi1", "msi2", "msi3",
|
|
"msi4", "msi5", "msi6", "msi7";
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0 0 0x7>;
|
|
interrupt-map = <0 0 0 1 &intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 0 0 2 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 0 0 3 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 0 0 4 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
|
|
<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
|
|
<&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
|
|
<&gcc GCC_PCIE_1_SLV_AXI_CLK>,
|
|
<&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>;
|
|
|
|
clock-names = "aux",
|
|
"cfg",
|
|
"bus_master",
|
|
"bus_slave",
|
|
"slave_q2a";
|
|
|
|
assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
|
|
assigned-clock-rates = <19200000>;
|
|
|
|
interconnects = <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>,
|
|
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>;
|
|
interconnect-names = "pcie-mem", "cpu-pcie";
|
|
|
|
iommu-map = <0x0 &pcie_smmu 0x0080 0x1>,
|
|
<0x100 &pcie_smmu 0x0081 0x1>;
|
|
|
|
resets = <&gcc GCC_PCIE_1_BCR>;
|
|
reset-names = "pci";
|
|
power-domains = <&gcc PCIE_1_GDSC>;
|
|
|
|
phys = <&pcie1_phy>;
|
|
phy-names = "pciephy";
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
pcie1_phy: phy@1c14000 {
|
|
compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy";
|
|
reg = <0x0 0x1c14000 0x0 0x4000>;
|
|
|
|
clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
|
|
<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
|
|
<&gcc GCC_PCIE_CLKREF_EN>,
|
|
<&gcc GCC_PCIE_1_PHY_RCHNG_CLK>,
|
|
<&gcc GCC_PCIE_1_PIPE_CLK>,
|
|
<&gcc GCC_PCIE_1_PIPEDIV2_CLK>,
|
|
<&gcc GCC_PCIE_1_PHY_AUX_CLK>;
|
|
|
|
clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe",
|
|
"pipediv2", "phy_aux";
|
|
|
|
assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
|
|
assigned-clock-rates = <100000000>;
|
|
|
|
resets = <&gcc GCC_PCIE_1_PHY_BCR>;
|
|
reset-names = "phy";
|
|
|
|
#clock-cells = <0>;
|
|
clock-output-names = "pcie_1_pipe_clk";
|
|
|
|
#phy-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
};
|