214 lines
4.5 KiB
Plaintext
214 lines
4.5 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
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/*
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* Copyright (c) 2022 TQ-Systems GmbH <linux@ew.tq-group.com>,
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* D-82229 Seefeld, Germany.
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* Author: Markus Niebel
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*/
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#include "imx93.dtsi"
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/{
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model = "TQ-Systems i.MX93 TQMa93xxLA/TQMa93xxCA SOM";
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compatible = "tq,imx93-tqma9352", "fsl,imx93";
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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linux,cma {
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compatible = "shared-dma-pool";
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reusable;
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alloc-ranges = <0 0x60000000 0 0x40000000>;
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size = <0 0x10000000>;
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linux,cma-default;
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};
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};
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reg_v1v8: regulator-v1v8 {
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compatible = "regulator-fixed";
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regulator-name = "V_1V8";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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};
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reg_v3v3: regulator-v3v3 {
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compatible = "regulator-fixed";
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regulator-name = "V_3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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/* SD2 RST# via PMIC SW_EN */
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reg_usdhc2_vmmc: regulator-usdhc2 {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
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regulator-name = "VSD_3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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vin-supply = <®_v3v3>;
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gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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};
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&adc1 {
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vref-supply = <®_v1v8>;
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};
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&flexspi1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexspi1>;
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status = "okay";
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flash0: flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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/*
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* no DQS, RXCLKSRC internal loop back, max 66 MHz
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* clk framework uses CLK_DIVIDER_ROUND_CLOSEST
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* selected value together with root from
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* IMX93_CLK_SYS_PLL_PFD1 @ 800.000.000 Hz helps to
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* respect the maximum value.
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*/
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spi-max-frequency = <62000000>;
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spi-tx-bus-width = <4>;
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spi-rx-bus-width = <4>;
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};
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};
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&gpio1 {
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pmic-irq-hog {
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gpio-hog;
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gpios = <3 GPIO_ACTIVE_LOW>;
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input;
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line-name = "PMIC_IRQ#";
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};
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};
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&lpi2c1 {
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clock-frequency = <400000>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&pinctrl_lpi2c1>;
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pinctrl-1 = <&pinctrl_lpi2c1>;
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status = "okay";
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se97_som: temperature-sensor@1b {
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compatible = "nxp,se97b", "jedec,jc-42.4-temp";
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reg = <0x1b>;
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};
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pcf85063: rtc@51 {
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compatible = "nxp,pcf85063a";
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reg = <0x51>;
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quartz-load-femtofarads = <7000>;
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};
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eeprom0: eeprom@53 {
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compatible = "nxp,se97b", "atmel,24c02";
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reg = <0x53>;
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pagesize = <16>;
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read-only;
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vcc-supply = <®_v3v3>;
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};
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eeprom1: eeprom@57 {
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compatible = "atmel,24c64";
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reg = <0x57>;
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pagesize = <32>;
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vcc-supply = <®_v3v3>;
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};
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/* protectable identification memory (part of M24C64-D @57) */
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eeprom@5f {
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compatible = "st,24c64", "atmel,24c64";
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reg = <0x5f>;
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size = <32>;
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pagesize = <32>;
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vcc-supply = <®_v3v3>;
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};
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imu@6a {
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compatible = "st,ism330dhcx";
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reg = <0x6a>;
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vdd-supply = <®_v3v3>;
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vddio-supply = <®_v3v3>;
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};
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};
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&usdhc1 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc1>;
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pinctrl-1 = <&pinctrl_usdhc1>;
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pinctrl-2 = <&pinctrl_usdhc1>;
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bus-width = <8>;
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non-removable;
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no-sdio;
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no-sd;
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status = "okay";
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};
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&wdog3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_wdog>;
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status = "okay";
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};
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&iomuxc {
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pinctrl_flexspi1: flexspi1grp {
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fsl,pins = <
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MX93_PAD_SD3_CMD__FLEXSPI1_A_SS0_B 0x3fe
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MX93_PAD_SD3_CLK__FLEXSPI1_A_SCLK 0x3fe
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MX93_PAD_SD3_DATA0__FLEXSPI1_A_DATA00 0x3fe
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MX93_PAD_SD3_DATA1__FLEXSPI1_A_DATA01 0x3fe
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MX93_PAD_SD3_DATA2__FLEXSPI1_A_DATA02 0x3fe
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MX93_PAD_SD3_DATA3__FLEXSPI1_A_DATA03 0x3fe
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>;
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};
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pinctrl_lpi2c1: lpi2c1grp {
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fsl,pins = <
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MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e
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MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e
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>;
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};
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pinctrl_pca9451: pca9451grp {
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fsl,pins = <
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MX93_PAD_I2C2_SDA__GPIO1_IO03 0x1306
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>;
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};
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pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
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fsl,pins = <
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MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x1306
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>;
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};
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pinctrl_usdhc1: usdhc1grp {
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fsl,pins = <
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/* HYS | PU | PD | FSEL_3 | X5 */
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MX93_PAD_SD1_CLK__USDHC1_CLK 0x17be
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MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x17be
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/* HYS | PU | FSEL_3 | X5 */
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MX93_PAD_SD1_CMD__USDHC1_CMD 0x13be
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/* HYS | PU | FSEL_3 | X4 */
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MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x139e
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MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x139e
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MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x139e
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MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x139e
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MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x139e
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MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x139e
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MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x139e
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MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x139e
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>;
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};
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pinctrl_wdog: wdoggrp {
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fsl,pins = <
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MX93_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x31e
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>;
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};
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};
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