435 lines
9.0 KiB
Plaintext
435 lines
9.0 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2018-2019 NXP
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* Dong Aisheng <aisheng.dong@nxp.com>
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*/
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#include <dt-bindings/clock/imx8-lpcg.h>
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#include <dt-bindings/firmware/imx/rsrc.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/pinctrl/pads-imx8qm.h>
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#include <dt-bindings/thermal/thermal.h>
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/ {
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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mmc0 = &usdhc1;
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mmc1 = &usdhc2;
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mmc2 = &usdhc3;
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serial0 = &lpuart0;
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serial1 = &lpuart1;
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serial2 = &lpuart2;
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serial3 = &lpuart3;
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vpu-core0 = &vpu_core0;
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vpu-core1 = &vpu_core1;
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vpu-core2 = &vpu_core2;
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};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&A53_0>;
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};
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core1 {
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cpu = <&A53_1>;
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};
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core2 {
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cpu = <&A53_2>;
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};
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core3 {
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cpu = <&A53_3>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&A72_0>;
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};
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core1 {
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cpu = <&A72_1>;
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};
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};
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};
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A53_0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x0>;
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clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>;
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enable-method = "psci";
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i-cache-size = <0x8000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <128>;
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next-level-cache = <&A53_L2>;
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operating-points-v2 = <&a53_opp_table>;
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#cooling-cells = <2>;
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};
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A53_1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x1>;
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clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>;
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enable-method = "psci";
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i-cache-size = <0x8000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <128>;
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next-level-cache = <&A53_L2>;
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operating-points-v2 = <&a53_opp_table>;
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#cooling-cells = <2>;
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};
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A53_2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x2>;
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clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>;
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enable-method = "psci";
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i-cache-size = <0x8000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <128>;
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next-level-cache = <&A53_L2>;
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operating-points-v2 = <&a53_opp_table>;
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#cooling-cells = <2>;
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};
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A53_3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x3>;
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clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>;
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enable-method = "psci";
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i-cache-size = <0x8000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <128>;
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next-level-cache = <&A53_L2>;
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operating-points-v2 = <&a53_opp_table>;
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#cooling-cells = <2>;
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};
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A72_0: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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reg = <0x0 0x100>;
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clocks = <&clk IMX_SC_R_A72 IMX_SC_PM_CLK_CPU>;
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enable-method = "psci";
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i-cache-size = <0xC000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <256>;
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next-level-cache = <&A72_L2>;
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operating-points-v2 = <&a72_opp_table>;
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#cooling-cells = <2>;
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};
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A72_1: cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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reg = <0x0 0x101>;
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clocks = <&clk IMX_SC_R_A72 IMX_SC_PM_CLK_CPU>;
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enable-method = "psci";
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next-level-cache = <&A72_L2>;
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operating-points-v2 = <&a72_opp_table>;
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#cooling-cells = <2>;
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};
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A53_L2: l2-cache0 {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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cache-size = <0x100000>;
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cache-line-size = <64>;
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cache-sets = <1024>;
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};
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A72_L2: l2-cache1 {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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cache-size = <0x100000>;
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cache-line-size = <64>;
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cache-sets = <1024>;
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};
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};
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a53_opp_table: opp-table-0 {
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compatible = "operating-points-v2";
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opp-shared;
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opp-600000000 {
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opp-hz = /bits/ 64 <600000000>;
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opp-microvolt = <900000>;
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clock-latency-ns = <150000>;
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};
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opp-896000000 {
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opp-hz = /bits/ 64 <896000000>;
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opp-microvolt = <1000000>;
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clock-latency-ns = <150000>;
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};
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opp-1104000000 {
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opp-hz = /bits/ 64 <1104000000>;
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opp-microvolt = <1100000>;
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clock-latency-ns = <150000>;
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};
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opp-1200000000 {
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opp-hz = /bits/ 64 <1200000000>;
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opp-microvolt = <1100000>;
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clock-latency-ns = <150000>;
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opp-suspend;
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};
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};
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a72_opp_table: opp-table-1 {
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compatible = "operating-points-v2";
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opp-shared;
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opp-600000000 {
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opp-hz = /bits/ 64 <600000000>;
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opp-microvolt = <1000000>;
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clock-latency-ns = <150000>;
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};
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opp-1056000000 {
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opp-hz = /bits/ 64 <1056000000>;
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opp-microvolt = <1000000>;
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clock-latency-ns = <150000>;
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};
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opp-1296000000 {
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opp-hz = /bits/ 64 <1296000000>;
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opp-microvolt = <1100000>;
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clock-latency-ns = <150000>;
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};
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opp-1596000000 {
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opp-hz = /bits/ 64 <1596000000>;
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opp-microvolt = <1100000>;
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clock-latency-ns = <150000>;
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opp-suspend;
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};
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};
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gic: interrupt-controller@51a00000 {
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compatible = "arm,gic-v3";
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reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
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<0x0 0x51b00000 0 0xC0000>, /* GICR */
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<0x0 0x52000000 0 0x2000>, /* GICC */
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<0x0 0x52010000 0 0x1000>, /* GICH */
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<0x0 0x52020000 0 0x20000>; /* GICV */
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#interrupt-cells = <3>;
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interrupt-controller;
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&gic>;
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};
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pmu {
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compatible = "arm,armv8-pmuv3";
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
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};
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system-controller {
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compatible = "fsl,imx-scu";
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mbox-names = "tx0",
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"rx0",
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"gip3";
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mboxes = <&lsio_mu1 0 0
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&lsio_mu1 1 0
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&lsio_mu1 3 3>;
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pd: power-controller {
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compatible = "fsl,imx8qm-scu-pd", "fsl,scu-pd";
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#power-domain-cells = <1>;
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};
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clk: clock-controller {
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compatible = "fsl,imx8qm-clk", "fsl,scu-clk";
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#clock-cells = <2>;
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};
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iomuxc: pinctrl {
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compatible = "fsl,imx8qm-iomuxc";
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};
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rtc: rtc {
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compatible = "fsl,imx8qxp-sc-rtc";
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};
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tsens: thermal-sensor {
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compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal";
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#thermal-sensor-cells = <1>;
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};
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};
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thermal-zones {
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cpu0-thermal {
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polling-delay-passive = <250>;
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polling-delay = <2000>;
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thermal-sensors = <&tsens IMX_SC_R_A53>;
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trips {
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cpu_alert0: trip0 {
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temperature = <107000>;
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hysteresis = <2000>;
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type = "passive";
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};
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cpu_crit0: trip1 {
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temperature = <127000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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cooling-maps {
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map0 {
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trip = <&cpu_alert0>;
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cooling-device =
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<&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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};
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};
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};
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cpu1-thermal {
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polling-delay-passive = <250>;
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polling-delay = <2000>;
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thermal-sensors = <&tsens IMX_SC_R_A72>;
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trips {
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cpu_alert1: trip0 {
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temperature = <107000>;
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hysteresis = <2000>;
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type = "passive";
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};
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cpu_crit1: trip1 {
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temperature = <127000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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cooling-maps {
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map0 {
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trip = <&cpu_alert1>;
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cooling-device =
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<&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&A72_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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};
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};
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};
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gpu0-thermal {
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polling-delay-passive = <250>;
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polling-delay = <2000>;
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thermal-sensors = <&tsens IMX_SC_R_GPU_0_PID0>;
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trips {
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gpu_alert0: trip0 {
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temperature = <107000>;
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hysteresis = <2000>;
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type = "passive";
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};
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gpu_crit0: trip1 {
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temperature = <127000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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};
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gpu1-thermal {
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polling-delay-passive = <250>;
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polling-delay = <2000>;
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thermal-sensors = <&tsens IMX_SC_R_GPU_1_PID0>;
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trips {
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gpu_alert1: trip0 {
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temperature = <107000>;
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hysteresis = <2000>;
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type = "passive";
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};
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gpu_crit1: trip1 {
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temperature = <127000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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};
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drc0-thermal {
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polling-delay-passive = <250>;
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polling-delay = <2000>;
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thermal-sensors = <&tsens IMX_SC_R_DRC_0>;
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trips {
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drc_alert0: trip0 {
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temperature = <107000>;
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hysteresis = <2000>;
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type = "passive";
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};
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drc_crit0: trip1 {
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temperature = <127000>;
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hysteresis = <2000>;
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type = "critical";
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};
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};
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};
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};
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/* sorted in register address */
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#include "imx8-ss-vpu.dtsi"
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#include "imx8-ss-img.dtsi"
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#include "imx8-ss-dma.dtsi"
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#include "imx8-ss-conn.dtsi"
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#include "imx8-ss-lsio.dtsi"
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};
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#include "imx8qm-ss-img.dtsi"
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#include "imx8qm-ss-dma.dtsi"
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#include "imx8qm-ss-conn.dtsi"
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#include "imx8qm-ss-lsio.dtsi"
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