122 lines
2.4 KiB
Plaintext
122 lines
2.4 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2021 BSH
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*/
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/ {
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backlight: backlight {
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compatible = "pwm-backlight";
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pwms = <&pwm1 0 700000 0>; /* 700000 ns = 1337Hz */
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brightness-levels = <0 100>;
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num-interpolated-steps = <100>;
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default-brightness-level = <50>;
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status = "okay";
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};
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reg_3v3_dvdd: regulator-3v3-O3 {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_dvdd>;
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regulator-name = "3v3-dvdd-supply";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio1 7 GPIO_ACTIVE_LOW>;
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};
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reg_v3v3_avdd: regulator-3v3-O2 {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_avdd>;
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regulator-name = "3v3-avdd-supply";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio1 5 GPIO_ACTIVE_LOW>;
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};
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};
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&pwm1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_bl>;
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status = "okay";
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};
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&lcdif {
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assigned-clocks = <&clk IMX8MN_VIDEO_PLL1>;
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assigned-clock-rates = <594000000>;
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status = "okay";
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};
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&pgc_dispmix {
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assigned-clocks = <&clk IMX8MN_CLK_DISP_AXI>, <&clk IMX8MN_CLK_DISP_APB>;
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assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_1000M>, <&clk IMX8MN_SYS_PLL1_800M>;
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assigned-clock-rates = <500000000>, <200000000>;
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};
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&mipi_dsi {
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#address-cells = <1>;
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#size-cells = <0>;
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samsung,esc-clock-frequency = <20000000>;
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samsung,pll-clock-frequency = <12000000>;
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status = "okay";
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panel@0 {
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compatible = "sharp,ls068b3sx02", "syna,r63353";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_panel>;
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reg = <0>;
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backlight = <&backlight>;
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dvdd-supply = <®_3v3_dvdd>;
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avdd-supply = <®_v3v3_avdd>;
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reset-gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
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port {
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panel_in: endpoint {
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remote-endpoint = <&mipi_dsi_out>;
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};
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};
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};
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ports {
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port@1 {
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reg = <1>;
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mipi_dsi_out: endpoint {
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remote-endpoint = <&panel_in>;
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};
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};
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};
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};
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&gpu {
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status = "okay";
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};
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&iomuxc {
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pinctrl_avdd: avddgrp {
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fsl,pins = <
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MX8MN_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x16 /* VDD 3V3_VO2 */
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>;
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};
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/* This is for both PWM and voltage regulators for display */
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pinctrl_bl: blgrp {
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fsl,pins = <
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MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x16
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>;
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};
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pinctrl_dvdd: dvddgrp {
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fsl,pins = <
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MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x16 /* VDD 3V3_VO3 */
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>;
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};
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pinctrl_panel: panelgrp {
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fsl,pins = <
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MX8MN_IOMUXC_SAI3_RXC_GPIO4_IO29 0x16 /* panel reset */
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>;
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};
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};
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