70 lines
1.7 KiB
Plaintext
70 lines
1.7 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* Samsung's Exynos3250 based ARTIK5 evaluation board device tree source
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*
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* Copyright (c) 2016 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Device tree source file for Samsung's ARTIK5 evaluation board
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* which is based on Samsung Exynos3250 SoC.
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*/
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/dts-v1/;
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#include "exynos3250-artik5.dtsi"
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/ {
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model = "Samsung ARTIK5 evaluation board";
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compatible = "samsung,artik5-eval", "samsung,artik5",
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"samsung,exynos3250", "samsung,exynos3";
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aliases {
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mmc0 = &mshc_2;
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};
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};
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&mshc_2 {
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cap-sd-highspeed;
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disable-wp;
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vqmmc-supply = <&ldo3_reg>;
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card-detect-delay = <200>;
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clock-frequency = <100000000>;
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max-frequency = <100000000>;
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samsung,dw-mshc-ciu-div = <1>;
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samsung,dw-mshc-sdr-timing = <0 1>;
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samsung,dw-mshc-ddr-timing = <1 2>;
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pinctrl-names = "default";
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pinctrl-0 = <&sd2_cmd &sd2_clk &sd2_cd &sd2_bus1 &sd2_bus4>;
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bus-width = <4>;
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status = "okay";
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};
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&serial_2 {
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status = "okay";
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};
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&spi_0 {
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status = "okay";
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cs-gpios = <&gpx3 4 GPIO_ACTIVE_LOW>, <0>;
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assigned-clocks = <&cmu CLK_MOUT_SPI0>, <&cmu CLK_DIV_SPI0>,
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<&cmu CLK_DIV_SPI0_PRE>, <&cmu CLK_SCLK_SPI0>;
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assigned-clock-parents = <&cmu CLK_DIV_MPLL_PRE>, /* for: CLK_MOUT_SPI0 */
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<&cmu CLK_MOUT_SPI0>, /* for: CLK_DIV_SPI0 */
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<&cmu CLK_DIV_SPI0>, /* for: CLK_DIV_SPI0_PRE */
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<&cmu CLK_DIV_SPI0_PRE>; /* for: CLK_SCLK_SPI0 */
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ethernet@0 {
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compatible = "asix,ax88796c";
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reg = <0x0>;
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local-mac-address = [00 00 00 00 00 00]; /* Filled in by a boot-loader */
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interrupt-parent = <&gpx2>;
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interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
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spi-max-frequency = <40000000>;
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reset-gpios = <&gpe0 2 GPIO_ACTIVE_LOW>;
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controller-data {
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samsung,spi-feedback-delay = <2>;
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};
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};
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};
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