814 lines
19 KiB
Plaintext
814 lines
19 KiB
Plaintext
// SPDX-License-Identifier: BSD-3-Clause
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/*
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* SDX65 SoC device tree source
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*
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* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
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*
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*/
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#include <dt-bindings/clock/qcom,gcc-sdx65.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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#include <dt-bindings/soc/qcom,rpmh-rsc.h>
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#include <dt-bindings/interconnect/qcom,sdx65.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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qcom,msm-id = <458 0x10000>, <483 0x10000>, <509 0x10000>;
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interrupt-parent = <&intc>;
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memory {
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device_type = "memory";
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reg = <0 0>;
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};
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clocks {
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xo_board: xo-board {
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compatible = "fixed-clock";
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clock-frequency = <76800000>;
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clock-output-names = "xo_board";
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#clock-cells = <0>;
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};
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sleep_clk: sleep-clk {
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compatible = "fixed-clock";
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clock-frequency = <32764>;
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clock-output-names = "sleep_clk";
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#clock-cells = <0>;
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};
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nand_clk_dummy: nand-clk-dummy {
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compatible = "fixed-clock";
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clock-frequency = <32764>;
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#clock-cells = <0>;
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};
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x0>;
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enable-method = "psci";
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clocks = <&apcs>;
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power-domains = <&rpmhpd SDX65_CX_AO>;
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power-domain-names = "rpmhpd";
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operating-points-v2 = <&cpu_opp_table>;
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};
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};
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firmware {
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scm {
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compatible = "qcom,scm-sdx65", "qcom,scm";
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};
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};
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mc_virt: interconnect-mc-virt {
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compatible = "qcom,sdx65-mc-virt";
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#interconnect-cells = <1>;
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qcom,bcm-voters = <&apps_bcm_voter>;
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};
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cpu_opp_table: opp-table-cpu {
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compatible = "operating-points-v2";
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opp-shared;
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opp-345600000 {
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opp-hz = /bits/ 64 <345600000>;
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required-opps = <&rpmhpd_opp_low_svs>;
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};
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opp-576000000 {
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opp-hz = /bits/ 64 <576000000>;
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required-opps = <&rpmhpd_opp_svs>;
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};
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opp-1094400000 {
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opp-hz = /bits/ 64 <1094400000>;
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required-opps = <&rpmhpd_opp_nom>;
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};
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opp-1497600000 {
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opp-hz = /bits/ 64 <1497600000>;
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required-opps = <&rpmhpd_opp_turbo>;
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};
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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reserved_memory: reserved-memory {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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tz_heap_mem: memory@8fcad000 {
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no-map;
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reg = <0x8fcad000 0x40000>;
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};
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secdata_mem: memory@8fcfd000 {
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no-map;
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reg = <0x8fcfd000 0x1000>;
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};
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hyp_mem: memory@8fd00000 {
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no-map;
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reg = <0x8fd00000 0x80000>;
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};
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access_control_mem: memory@8fd80000 {
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no-map;
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reg = <0x8fd80000 0x80000>;
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};
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aop_mem: memory@8fe00000 {
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no-map;
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reg = <0x8fe00000 0x20000>;
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};
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smem_mem: memory@8fe20000 {
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compatible = "qcom,smem";
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reg = <0x8fe20000 0xc0000>;
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hwlocks = <&tcsr_mutex 3>;
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no-map;
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};
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cmd_db: reserved-memory@8fee0000 {
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compatible = "qcom,cmd-db";
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reg = <0x8fee0000 0x20000>;
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no-map;
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};
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tz_mem: memory@8ff00000 {
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no-map;
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reg = <0x8ff00000 0x100000>;
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};
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tz_apps_mem: memory@90000000 {
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no-map;
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reg = <0x90000000 0x500000>;
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};
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llcc_tcm_mem: memory@15800000 {
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no-map;
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reg = <0x15800000 0x800000>;
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};
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};
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smp2p-mpss {
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compatible = "qcom,smp2p";
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qcom,smem = <435>, <428>;
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interrupts = <GIC_SPI 113 IRQ_TYPE_EDGE_RISING>;
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mboxes = <&apcs 14>;
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qcom,local-pid = <0>;
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qcom,remote-pid = <1>;
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modem_smp2p_out: master-kernel {
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qcom,entry-name = "master-kernel";
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#qcom,smem-state-cells = <1>;
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};
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modem_smp2p_in: slave-kernel {
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qcom,entry-name = "slave-kernel";
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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ipa_smp2p_out: ipa-ap-to-modem {
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qcom,entry-name = "ipa";
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#qcom,smem-state-cells = <1>;
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};
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ipa_smp2p_in: ipa-modem-to-ap {
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qcom,entry-name = "ipa";
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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soc: soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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compatible = "simple-bus";
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gcc: clock-controller@100000 {
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compatible = "qcom,gcc-sdx65";
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reg = <0x00100000 0x001f7400>;
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&rpmhcc RPMH_CXO_CLK_A>,
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<&sleep_clk>,
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<&pcie_phy>,
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<0>;
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clock-names = "bi_tcxo",
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"bi_tcxo_ao",
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"sleep_clk",
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"pcie_pipe_clk",
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"usb3_phy_wrapper_gcc_usb30_pipe_clk";
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#power-domain-cells = <1>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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blsp1_uart3: serial@831000 {
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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reg = <0x00831000 0x200>;
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interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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status = "disabled";
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};
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usb_hsphy: phy@ff4000 {
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compatible = "qcom,sdx65-usb-hs-phy",
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"qcom,usb-snps-hs-7nm-phy";
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reg = <0xff4000 0x120>;
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#phy-cells = <0>;
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clocks = <&rpmhcc RPMH_CXO_CLK>;
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clock-names = "ref";
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resets = <&gcc GCC_QUSB2PHY_BCR>;
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status = "disabled";
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};
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usb_qmpphy: phy@ff6000 {
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compatible = "qcom,sdx65-qmp-usb3-uni-phy";
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reg = <0x00ff6000 0x2000>;
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clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
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<&gcc GCC_USB3_PRIM_CLKREF_EN>,
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<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
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<&gcc GCC_USB3_PHY_PIPE_CLK>;
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clock-names = "aux",
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"ref",
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"cfg_ahb",
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"pipe";
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clock-output-names = "usb3_uni_phy_pipe_clk_src";
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#clock-cells = <0>;
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#phy-cells = <0>;
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resets = <&gcc GCC_USB3_PHY_BCR>,
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<&gcc GCC_USB3PHY_PHY_BCR>;
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reset-names = "phy",
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"phy_phy";
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status = "disabled";
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};
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system_noc: interconnect@1620000 {
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compatible = "qcom,sdx65-system-noc";
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reg = <0x01620000 0x31200>;
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#interconnect-cells = <1>;
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qcom,bcm-voters = <&apps_bcm_voter>;
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};
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qpic_bam: dma-controller@1b04000 {
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compatible = "qcom,bam-v1.7.0";
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reg = <0x01b04000 0x1c000>;
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interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&rpmhcc RPMH_QPIC_CLK>;
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clock-names = "bam_clk";
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#dma-cells = <1>;
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qcom,ee = <0>;
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qcom,controlled-remotely;
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status = "disabled";
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};
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qpic_nand: nand-controller@1b30000 {
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compatible = "qcom,sdx55-nand";
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reg = <0x01b30000 0x10000>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&rpmhcc RPMH_QPIC_CLK>,
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<&nand_clk_dummy>;
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clock-names = "core", "aon";
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dmas = <&qpic_bam 0>,
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<&qpic_bam 1>,
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<&qpic_bam 2>;
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dma-names = "tx", "rx", "cmd";
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status = "disabled";
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};
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pcie_ep: pcie-ep@1c00000 {
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compatible = "qcom,sdx65-pcie-ep", "qcom,sdx55-pcie-ep";
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reg = <0x01c00000 0x3000>,
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<0x40000000 0xf1d>,
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<0x40000f20 0xa8>,
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<0x40001000 0x1000>,
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<0x40200000 0x100000>,
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<0x01c03000 0x3000>;
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reg-names = "parf",
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"dbi",
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"elbi",
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"atu",
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"addr_space",
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"mmio";
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qcom,perst-regs = <&tcsr 0xb258 0xb270>;
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clocks = <&gcc GCC_PCIE_AUX_CLK>,
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<&gcc GCC_PCIE_CFG_AHB_CLK>,
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<&gcc GCC_PCIE_MSTR_AXI_CLK>,
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<&gcc GCC_PCIE_SLV_AXI_CLK>,
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<&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,
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<&gcc GCC_PCIE_SLEEP_CLK>,
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<&gcc GCC_PCIE_0_CLKREF_EN>;
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clock-names = "aux",
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"cfg",
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"bus_master",
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"bus_slave",
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"slave_q2a",
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"sleep",
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"ref";
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interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "global", "doorbell";
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resets = <&gcc GCC_PCIE_BCR>;
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reset-names = "core";
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power-domains = <&gcc PCIE_GDSC>;
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phys = <&pcie_phy>;
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phy-names = "pciephy";
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max-link-speed = <3>;
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num-lanes = <2>;
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status = "disabled";
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};
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pcie_phy: phy@1c06000 {
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compatible = "qcom,sdx65-qmp-gen4x2-pcie-phy";
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reg = <0x01c06000 0x2000>;
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clocks = <&gcc GCC_PCIE_AUX_PHY_CLK_SRC>,
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<&gcc GCC_PCIE_CFG_AHB_CLK>,
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<&gcc GCC_PCIE_0_CLKREF_EN>,
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<&gcc GCC_PCIE_RCHNG_PHY_CLK>,
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<&gcc GCC_PCIE_PIPE_CLK>;
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clock-names = "aux",
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"cfg_ahb",
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"ref",
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"rchng",
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"pipe";
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resets = <&gcc GCC_PCIE_PHY_BCR>;
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reset-names = "phy";
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assigned-clocks = <&gcc GCC_PCIE_RCHNG_PHY_CLK>;
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assigned-clock-rates = <100000000>;
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power-domains = <&gcc PCIE_GDSC>;
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#clock-cells = <0>;
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clock-output-names = "pcie_pipe_clk";
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#phy-cells = <0>;
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status = "disabled";
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};
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tcsr_mutex: hwlock@1f40000 {
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compatible = "qcom,tcsr-mutex";
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reg = <0x01f40000 0x40000>;
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#hwlock-cells = <1>;
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};
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tcsr: syscon@1fcb000 {
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compatible = "qcom,sdx65-tcsr", "syscon";
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reg = <0x01fc0000 0x1000>;
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};
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ipa: ipa@3f40000 {
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compatible = "qcom,sdx65-ipa";
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reg = <0x03f40000 0x10000>,
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<0x03f50000 0x5000>,
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<0x03e04000 0xfc000>;
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reg-names = "ipa-reg",
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"ipa-shared",
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"gsi";
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interrupts-extended = <&intc GIC_SPI 241 IRQ_TYPE_EDGE_RISING>,
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<&intc GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
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<&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
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<&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "ipa",
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"gsi",
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"ipa-clock-query",
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"ipa-setup-ready";
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iommus = <&apps_smmu 0x5e0 0x0>,
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<&apps_smmu 0x5e2 0x0>;
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clocks = <&rpmhcc RPMH_IPA_CLK>;
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clock-names = "core";
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interconnects = <&system_noc MASTER_IPA &mc_virt SLAVE_EBI1>,
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<&mem_noc MASTER_APPSS_PROC &system_noc SLAVE_IPA_CFG>;
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interconnect-names = "memory",
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"config";
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qcom,smem-states = <&ipa_smp2p_out 0>,
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<&ipa_smp2p_out 1>;
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qcom,smem-state-names = "ipa-clock-enabled-valid",
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"ipa-clock-enabled";
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status = "disabled";
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};
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remoteproc_mpss: remoteproc@4080000 {
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compatible = "qcom,sdx55-mpss-pas";
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reg = <0x04080000 0x4040>;
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interrupts-extended = <&intc GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
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<&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
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<&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
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<&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
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<&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
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<&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "wdog", "fatal", "ready", "handover",
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"stop-ack", "shutdown-ack";
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clocks = <&rpmhcc RPMH_CXO_CLK>;
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clock-names = "xo";
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power-domains = <&rpmhpd SDX65_CX>,
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<&rpmhpd SDX65_MSS>;
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power-domain-names = "cx", "mss";
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qcom,smem-states = <&modem_smp2p_out 0>;
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qcom,smem-state-names = "stop";
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status = "disabled";
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glink-edge {
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interrupts = <GIC_SPI 114 IRQ_TYPE_EDGE_RISING>;
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label = "mpss";
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qcom,remote-pid = <1>;
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mboxes = <&apcs 15>;
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};
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};
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sdhc_1: mmc@8804000 {
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compatible = "qcom,sdx65-sdhci", "qcom,sdhci-msm-v5";
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reg = <0x08804000 0x1000>;
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reg-names = "hc";
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interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "hc_irq", "pwr_irq";
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clocks = <&gcc GCC_SDCC1_AHB_CLK>,
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<&gcc GCC_SDCC1_APPS_CLK>;
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clock-names = "iface", "core";
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status = "disabled";
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};
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mem_noc: interconnect@9680000 {
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compatible = "qcom,sdx65-mem-noc";
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reg = <0x09680000 0x27200>;
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#interconnect-cells = <1>;
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qcom,bcm-voters = <&apps_bcm_voter>;
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};
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usb: usb@a6f8800 {
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compatible = "qcom,sdx65-dwc3", "qcom,dwc3";
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reg = <0x0a6f8800 0x400>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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clocks = <&gcc GCC_USB30_SLV_AHB_CLK>,
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<&gcc GCC_USB30_MASTER_CLK>,
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<&gcc GCC_USB30_MSTR_AXI_CLK>,
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<&gcc GCC_USB30_MOCK_UTMI_CLK>,
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<&gcc GCC_USB30_SLEEP_CLK>;
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clock-names = "cfg_noc", "core", "iface", "mock_utmi",
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"sleep";
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assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
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<&gcc GCC_USB30_MASTER_CLK>;
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assigned-clock-rates = <19200000>, <200000000>;
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|
|
|
interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
|
|
<&pdc 76 IRQ_TYPE_LEVEL_HIGH>,
|
|
<&pdc 18 IRQ_TYPE_EDGE_BOTH>,
|
|
<&pdc 19 IRQ_TYPE_EDGE_BOTH>;
|
|
interrupt-names = "hs_phy_irq",
|
|
"ss_phy_irq",
|
|
"dm_hs_phy_irq",
|
|
"dp_hs_phy_irq";
|
|
|
|
power-domains = <&gcc USB30_GDSC>;
|
|
|
|
resets = <&gcc GCC_USB30_BCR>;
|
|
|
|
status = "disabled";
|
|
|
|
usb_dwc3: usb@a600000 {
|
|
compatible = "snps,dwc3";
|
|
reg = <0x0a600000 0xcd00>;
|
|
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
|
|
iommus = <&apps_smmu 0x1a0 0x0>;
|
|
snps,dis_u2_susphy_quirk;
|
|
snps,dis_enblslpm_quirk;
|
|
phys = <&usb_hsphy>, <&usb_qmpphy>;
|
|
phy-names = "usb2-phy", "usb3-phy";
|
|
};
|
|
};
|
|
|
|
restart@c264000 {
|
|
compatible = "qcom,pshold";
|
|
reg = <0x0c264000 0x1000>;
|
|
};
|
|
|
|
spmi_bus: spmi@c440000 {
|
|
compatible = "qcom,spmi-pmic-arb";
|
|
reg = <0xc440000 0xd00>,
|
|
<0xc600000 0x2000000>,
|
|
<0xe600000 0x100000>,
|
|
<0xe700000 0xa0000>,
|
|
<0xc40a000 0x26000>;
|
|
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
|
|
interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "periph_irq";
|
|
interrupt-controller;
|
|
#interrupt-cells = <4>;
|
|
#address-cells = <2>;
|
|
#size-cells = <0>;
|
|
qcom,channel = <0>;
|
|
qcom,ee = <0>;
|
|
};
|
|
|
|
tlmm: pinctrl@f100000 {
|
|
compatible = "qcom,sdx65-tlmm";
|
|
reg = <0xf100000 0x300000>;
|
|
interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
gpio-ranges = <&tlmm 0 0 109>;
|
|
interrupt-controller;
|
|
interrupt-parent = <&intc>;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
pdc: interrupt-controller@b210000 {
|
|
compatible = "qcom,sdx65-pdc", "qcom,pdc";
|
|
reg = <0xb210000 0x10000>;
|
|
qcom,pdc-ranges = <0 147 52>, <52 266 32>;
|
|
#interrupt-cells = <2>;
|
|
interrupt-parent = <&intc>;
|
|
interrupt-controller;
|
|
};
|
|
|
|
sram@1468f000 {
|
|
compatible = "qcom,sdx65-imem", "syscon", "simple-mfd";
|
|
reg = <0x1468f000 0x1000>;
|
|
ranges = <0x0 0x1468f000 0x1000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
pil-reloc@94c {
|
|
compatible = "qcom,pil-reloc-info";
|
|
reg = <0x94c 0xc8>;
|
|
};
|
|
};
|
|
|
|
apps_smmu: iommu@15000000 {
|
|
compatible = "qcom,sdx65-smmu-500", "qcom,smmu-500", "arm,mmu-500";
|
|
reg = <0x15000000 0x40000>;
|
|
#iommu-cells = <2>;
|
|
#global-interrupts = <1>;
|
|
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
intc: interrupt-controller@17800000 {
|
|
compatible = "qcom,msm-qgic2";
|
|
interrupt-controller;
|
|
interrupt-parent = <&intc>;
|
|
#interrupt-cells = <3>;
|
|
reg = <0x17800000 0x1000>,
|
|
<0x17802000 0x1000>;
|
|
};
|
|
|
|
a7pll: clock@17808000 {
|
|
compatible = "qcom,sdx55-a7pll";
|
|
reg = <0x17808000 0x1000>;
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
|
clock-names = "bi_tcxo";
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
apcs: mailbox@17810000 {
|
|
compatible = "qcom,sdx55-apcs-gcc", "syscon";
|
|
reg = <0x17810000 0x2000>;
|
|
#mbox-cells = <1>;
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>, <&a7pll>, <&gcc GPLL0>;
|
|
clock-names = "ref", "pll", "aux";
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
watchdog@17817000 {
|
|
compatible = "qcom,apss-wdt-sdx65", "qcom,kpss-wdt";
|
|
reg = <0x17817000 0x1000>;
|
|
clocks = <&sleep_clk>;
|
|
};
|
|
|
|
timer@17820000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
compatible = "arm,armv7-timer-mem";
|
|
reg = <0x17820000 0x1000>;
|
|
clock-frequency = <19200000>;
|
|
|
|
frame@17821000 {
|
|
frame-number = <0>;
|
|
interrupts = <GIC_SPI 7 0x4>,
|
|
<GIC_SPI 6 0x4>;
|
|
reg = <0x17821000 0x1000>,
|
|
<0x17822000 0x1000>;
|
|
};
|
|
|
|
frame@17823000 {
|
|
frame-number = <1>;
|
|
interrupts = <GIC_SPI 8 0x4>;
|
|
reg = <0x17823000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17824000 {
|
|
frame-number = <2>;
|
|
interrupts = <GIC_SPI 9 0x4>;
|
|
reg = <0x17824000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17825000 {
|
|
frame-number = <3>;
|
|
interrupts = <GIC_SPI 10 0x4>;
|
|
reg = <0x17825000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17826000 {
|
|
frame-number = <4>;
|
|
interrupts = <GIC_SPI 11 0x4>;
|
|
reg = <0x17826000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17827000 {
|
|
frame-number = <5>;
|
|
interrupts = <GIC_SPI 12 0x4>;
|
|
reg = <0x17827000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17828000 {
|
|
frame-number = <6>;
|
|
interrupts = <GIC_SPI 13 0x4>;
|
|
reg = <0x17828000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17829000 {
|
|
frame-number = <7>;
|
|
interrupts = <GIC_SPI 14 0x4>;
|
|
reg = <0x17829000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
apps_rsc: rsc@17830000 {
|
|
label = "apps_rsc";
|
|
compatible = "qcom,rpmh-rsc";
|
|
reg = <0x17830000 0x10000>,
|
|
<0x17840000 0x10000>;
|
|
reg-names = "drv-0", "drv-1";
|
|
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
|
|
qcom,tcs-offset = <0xd00>;
|
|
qcom,drv-id = <1>;
|
|
qcom,tcs-config = <ACTIVE_TCS 2>,
|
|
<SLEEP_TCS 2>,
|
|
<WAKE_TCS 2>,
|
|
<CONTROL_TCS 1>;
|
|
|
|
rpmhcc: clock-controller {
|
|
compatible = "qcom,sdx65-rpmh-clk";
|
|
#clock-cells = <1>;
|
|
clock-names = "xo";
|
|
clocks = <&xo_board>;
|
|
};
|
|
|
|
rpmhpd: power-controller {
|
|
compatible = "qcom,sdx65-rpmhpd";
|
|
#power-domain-cells = <1>;
|
|
operating-points-v2 = <&rpmhpd_opp_table>;
|
|
|
|
rpmhpd_opp_table: opp-table {
|
|
compatible = "operating-points-v2";
|
|
|
|
rpmhpd_opp_ret: opp1 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
|
|
};
|
|
|
|
rpmhpd_opp_min_svs: opp2 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
|
|
};
|
|
|
|
rpmhpd_opp_low_svs: opp3 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
|
};
|
|
|
|
rpmhpd_opp_svs: opp4 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
|
|
};
|
|
|
|
rpmhpd_opp_svs_l1: opp5 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
|
|
};
|
|
|
|
rpmhpd_opp_nom: opp6 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
|
|
};
|
|
|
|
rpmhpd_opp_nom_l1: opp7 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
|
|
};
|
|
|
|
rpmhpd_opp_nom_l2: opp8 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
|
|
};
|
|
|
|
rpmhpd_opp_turbo: opp9 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
|
|
};
|
|
|
|
rpmhpd_opp_turbo_l1: opp10 {
|
|
opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
|
|
};
|
|
};
|
|
};
|
|
|
|
apps_bcm_voter: bcm-voter {
|
|
compatible = "qcom,bcm-voter";
|
|
};
|
|
|
|
};
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv7-timer";
|
|
interrupts = <1 13 0xf08>,
|
|
<1 12 0xf08>,
|
|
<1 10 0xf08>,
|
|
<1 11 0xf08>;
|
|
clock-frequency = <19200000>;
|
|
};
|
|
};
|