437 lines
10 KiB
Plaintext
437 lines
10 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/dts-v1/;
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/qcom,gcc-msm8660.h>
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#include <dt-bindings/soc/qcom,gsbi.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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model = "Qualcomm MSM8660";
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compatible = "qcom,msm8660";
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interrupt-parent = <&intc>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "qcom,scorpion";
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enable-method = "qcom,gcc-msm8660";
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device_type = "cpu";
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reg = <0>;
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next-level-cache = <&L2>;
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};
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cpu@1 {
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compatible = "qcom,scorpion";
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enable-method = "qcom,gcc-msm8660";
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device_type = "cpu";
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reg = <1>;
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next-level-cache = <&L2>;
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};
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L2: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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};
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};
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memory {
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device_type = "memory";
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reg = <0x0 0x0>;
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};
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cpu-pmu {
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compatible = "qcom,scorpion-mp-pmu";
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interrupts = <1 9 0x304>;
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};
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clocks {
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cxo_board: cxo-board-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <19200000>;
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clock-output-names = "cxo_board";
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};
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pxo_board: pxo-board-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <27000000>;
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clock-output-names = "pxo_board";
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};
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sleep-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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clock-output-names = "sleep_clk";
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};
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};
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soc: soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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compatible = "simple-bus";
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intc: interrupt-controller@2080000 {
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compatible = "qcom,msm-8660-qgic";
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interrupt-controller;
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#interrupt-cells = <3>;
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reg = < 0x02080000 0x1000 >,
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< 0x02081000 0x1000 >;
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};
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timer@2000000 {
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compatible = "qcom,scss-timer", "qcom,msm-timer";
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interrupts = <1 0 0x301>,
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<1 1 0x301>,
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<1 2 0x301>;
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reg = <0x02000000 0x100>;
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clock-frequency = <27000000>,
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<32768>;
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cpu-offset = <0x40000>;
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};
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tlmm: pinctrl@800000 {
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compatible = "qcom,msm8660-pinctrl";
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reg = <0x800000 0x4000>;
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gpio-controller;
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gpio-ranges = <&tlmm 0 0 173>;
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#gpio-cells = <2>;
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interrupts = <0 16 0x4>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gcc: clock-controller@900000 {
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compatible = "qcom,gcc-msm8660";
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#clock-cells = <1>;
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#power-domain-cells = <1>;
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#reset-cells = <1>;
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reg = <0x900000 0x4000>;
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clocks = <&pxo_board>, <&cxo_board>;
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clock-names = "pxo", "cxo";
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};
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gsbi1: gsbi@16000000 {
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compatible = "qcom,gsbi-v1.0.0";
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cell-index = <12>;
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reg = <0x16000000 0x100>;
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clocks = <&gcc GSBI1_H_CLK>;
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clock-names = "iface";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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syscon-tcsr = <&tcsr>;
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status = "disabled";
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gsbi1_spi: spi@16080000 {
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compatible = "qcom,spi-qup-v1.1.1";
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reg = <0x16080000 0x1000>;
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interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
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clock-names = "core", "iface";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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};
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gsbi3: gsbi@16200000 {
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compatible = "qcom,gsbi-v1.0.0";
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cell-index = <12>;
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reg = <0x16200000 0x100>;
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clocks = <&gcc GSBI3_H_CLK>;
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clock-names = "iface";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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syscon-tcsr = <&tcsr>;
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status = "disabled";
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gsbi3_i2c: i2c@16280000 {
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compatible = "qcom,i2c-qup-v1.1.1";
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reg = <0x16280000 0x1000>;
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interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GSBI3_QUP_CLK>, <&gcc GSBI3_H_CLK>;
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clock-names = "core", "iface";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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};
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gsbi6: gsbi@16500000 {
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compatible = "qcom,gsbi-v1.0.0";
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cell-index = <12>;
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reg = <0x16500000 0x100>;
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clocks = <&gcc GSBI6_H_CLK>;
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clock-names = "iface";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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status = "disabled";
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syscon-tcsr = <&tcsr>;
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gsbi6_serial: serial@16540000 {
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compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
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reg = <0x16540000 0x1000>,
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<0x16500000 0x1000>;
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interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
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clock-names = "core", "iface";
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status = "disabled";
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};
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gsbi6_i2c: i2c@16580000 {
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compatible = "qcom,i2c-qup-v1.1.1";
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reg = <0x16580000 0x1000>;
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interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;
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clock-names = "core", "iface";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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};
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gsbi7: gsbi@16600000 {
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compatible = "qcom,gsbi-v1.0.0";
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cell-index = <12>;
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reg = <0x16600000 0x100>;
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clocks = <&gcc GSBI7_H_CLK>;
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clock-names = "iface";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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status = "disabled";
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syscon-tcsr = <&tcsr>;
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gsbi7_serial: serial@16640000 {
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compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
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reg = <0x16640000 0x1000>,
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<0x16600000 0x1000>;
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interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
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clock-names = "core", "iface";
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status = "disabled";
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};
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gsbi7_i2c: i2c@16680000 {
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compatible = "qcom,i2c-qup-v1.1.1";
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reg = <0x16680000 0x1000>;
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interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>;
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clock-names = "core", "iface";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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};
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gsbi8: gsbi@19800000 {
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compatible = "qcom,gsbi-v1.0.0";
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cell-index = <12>;
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reg = <0x19800000 0x100>;
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clocks = <&gcc GSBI8_H_CLK>;
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clock-names = "iface";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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syscon-tcsr = <&tcsr>;
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status = "disabled";
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gsbi8_i2c: i2c@19880000 {
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compatible = "qcom,i2c-qup-v1.1.1";
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reg = <0x19880000 0x1000>;
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interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GSBI8_QUP_CLK>, <&gcc GSBI8_H_CLK>;
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clock-names = "core", "iface";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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};
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gsbi12: gsbi@19c00000 {
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compatible = "qcom,gsbi-v1.0.0";
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cell-index = <12>;
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reg = <0x19c00000 0x100>;
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clocks = <&gcc GSBI12_H_CLK>;
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clock-names = "iface";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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syscon-tcsr = <&tcsr>;
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gsbi12_serial: serial@19c40000 {
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compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
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reg = <0x19c40000 0x1000>,
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<0x19c00000 0x1000>;
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interrupts = <0 195 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>;
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clock-names = "core", "iface";
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status = "disabled";
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};
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gsbi12_i2c: i2c@19c80000 {
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compatible = "qcom,i2c-qup-v1.1.1";
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reg = <0x19c80000 0x1000>;
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interrupts = <0 196 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GSBI12_QUP_CLK>, <&gcc GSBI12_H_CLK>;
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clock-names = "core", "iface";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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};
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ebi2: external-bus@1a100000 {
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compatible = "qcom,msm8660-ebi2";
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#address-cells = <2>;
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#size-cells = <1>;
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ranges = <0 0x0 0x1a800000 0x00800000>,
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<1 0x0 0x1b000000 0x00800000>,
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<2 0x0 0x1b800000 0x00800000>,
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<3 0x0 0x1d000000 0x08000000>,
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<4 0x0 0x1c800000 0x00800000>,
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<5 0x0 0x1c000000 0x00800000>;
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reg = <0x1a100000 0x1000>, <0x1a110000 0x1000>;
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reg-names = "ebi2", "xmem";
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clocks = <&gcc EBI2_2X_CLK>, <&gcc EBI2_CLK>;
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clock-names = "ebi2x", "ebi2";
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status = "disabled";
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};
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ssbi: ssbi@500000 {
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compatible = "qcom,ssbi";
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reg = <0x500000 0x1000>;
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qcom,controller-type = "pmic-arbiter";
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};
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l2cc: clock-controller@2082000 {
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compatible = "qcom,kpss-gcc-msm8660", "qcom,kpss-gcc", "syscon";
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reg = <0x02082000 0x1000>;
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};
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rpm: rpm@104000 {
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compatible = "qcom,rpm-msm8660";
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reg = <0x00104000 0x1000>;
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qcom,ipc = <&l2cc 0x8 2>;
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interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "ack", "err", "wakeup";
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clocks = <&gcc RPM_MSG_RAM_H_CLK>;
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clock-names = "ram";
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rpmcc: clock-controller {
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compatible = "qcom,rpmcc-msm8660", "qcom,rpmcc";
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#clock-cells = <1>;
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clocks = <&pxo_board>;
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clock-names = "pxo";
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};
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};
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amba {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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sdcc1: mmc@12400000 {
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status = "disabled";
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compatible = "arm,pl18x", "arm,primecell";
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arm,primecell-periphid = <0x00051180>;
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reg = <0x12400000 0x8000>;
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interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
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clock-names = "mclk", "apb_pclk";
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bus-width = <8>;
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max-frequency = <48000000>;
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non-removable;
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cap-sd-highspeed;
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cap-mmc-highspeed;
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};
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sdcc2: mmc@12140000 {
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status = "disabled";
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compatible = "arm,pl18x", "arm,primecell";
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arm,primecell-periphid = <0x00051180>;
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reg = <0x12140000 0x8000>;
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interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>;
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clock-names = "mclk", "apb_pclk";
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bus-width = <8>;
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max-frequency = <48000000>;
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cap-sd-highspeed;
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cap-mmc-highspeed;
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};
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sdcc3: mmc@12180000 {
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compatible = "arm,pl18x", "arm,primecell";
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arm,primecell-periphid = <0x00051180>;
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status = "disabled";
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reg = <0x12180000 0x8000>;
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interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
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clock-names = "mclk", "apb_pclk";
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bus-width = <4>;
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cap-sd-highspeed;
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cap-mmc-highspeed;
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max-frequency = <48000000>;
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no-1-8-v;
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};
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sdcc4: mmc@121c0000 {
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compatible = "arm,pl18x", "arm,primecell";
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arm,primecell-periphid = <0x00051180>;
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status = "disabled";
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reg = <0x121c0000 0x8000>;
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interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
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clock-names = "mclk", "apb_pclk";
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bus-width = <4>;
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max-frequency = <48000000>;
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cap-sd-highspeed;
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cap-mmc-highspeed;
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};
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sdcc5: mmc@12200000 {
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compatible = "arm,pl18x", "arm,primecell";
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arm,primecell-periphid = <0x00051180>;
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status = "disabled";
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reg = <0x12200000 0x8000>;
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interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc SDC5_CLK>, <&gcc SDC5_H_CLK>;
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clock-names = "mclk", "apb_pclk";
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bus-width = <4>;
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cap-sd-highspeed;
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cap-mmc-highspeed;
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max-frequency = <48000000>;
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};
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};
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tcsr: syscon@1a400000 {
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compatible = "qcom,tcsr-msm8660", "syscon";
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reg = <0x1a400000 0x100>;
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};
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};
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};
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