145 lines
3.9 KiB
Plaintext
145 lines
3.9 KiB
Plaintext
#include "bcm283x.dtsi"
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#include "bcm2835-common.dtsi"
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/ {
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compatible = "brcm,bcm2837";
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soc {
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ranges = <0x7e000000 0x3f000000 0x1000000>,
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<0x40000000 0x40000000 0x00001000>;
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dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
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local_intc: local_intc@40000000 {
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compatible = "brcm,bcm2836-l1-intc";
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reg = <0x40000000 0x100>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&local_intc>;
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};
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};
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arm-pmu {
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compatible = "arm,cortex-a53-pmu";
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interrupt-parent = <&local_intc>;
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interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupt-parent = <&local_intc>;
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interrupts = <0 IRQ_TYPE_LEVEL_HIGH>, // PHYS_SECURE_PPI
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<1 IRQ_TYPE_LEVEL_HIGH>, // PHYS_NONSECURE_PPI
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<3 IRQ_TYPE_LEVEL_HIGH>, // VIRT_PPI
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<2 IRQ_TYPE_LEVEL_HIGH>; // HYP_PPI
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always-on;
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};
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cpus: cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit
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/* Source for d/i-cache-line-size and d/i-cache-sets
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* https://developer.arm.com/documentation/ddi0500/e/level-1-memory-system
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* /about-the-l1-memory-system?lang=en
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*
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* Source for d/i-cache-size
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* https://magpi.raspberrypi.com/articles/raspberry-pi-3-specs-benchmarks
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*/
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0>;
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enable-method = "spin-table";
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cpu-release-addr = <0x0 0x000000d8>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
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i-cache-size = <0x8000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
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next-level-cache = <&l2>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <1>;
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enable-method = "spin-table";
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cpu-release-addr = <0x0 0x000000e0>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
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i-cache-size = <0x8000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
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next-level-cache = <&l2>;
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <2>;
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enable-method = "spin-table";
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cpu-release-addr = <0x0 0x000000e8>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
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i-cache-size = <0x8000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
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next-level-cache = <&l2>;
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <3>;
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enable-method = "spin-table";
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cpu-release-addr = <0x0 0x000000f0>;
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d-cache-size = <0x8000>;
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d-cache-line-size = <64>;
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d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
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i-cache-size = <0x8000>;
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i-cache-line-size = <64>;
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i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
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next-level-cache = <&l2>;
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};
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/* Source for cache-line-size + cache-sets
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* https://developer.arm.com/documentation/ddi0500
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* /e/level-2-memory-system/about-the-l2-memory-system?lang=en
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* Source for cache-size
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* https://datasheets.raspberrypi.com/cm/cm1-and-cm3-datasheet.pdf
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*/
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l2: l2-cache0 {
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compatible = "cache";
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cache-unified;
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cache-size = <0x80000>;
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cache-line-size = <64>;
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cache-sets = <512>; // 512KiB(size)/64(line-size)=8192ways/16-way set
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cache-level = <2>;
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};
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};
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};
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/* Make the BCM2835-style global interrupt controller be a child of the
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* CPU-local interrupt controller.
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*/
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&intc {
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compatible = "brcm,bcm2836-armctrl-ic";
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reg = <0x7e00b200 0x200>;
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interrupt-parent = <&local_intc>;
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interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
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};
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&cpu_thermal {
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coefficients = <(-538) 412000>;
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};
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/* enable thermal sensor with the correct compatible property set */
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&thermal {
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compatible = "brcm,bcm2837-thermal";
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status = "okay";
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};
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