121 lines
3.7 KiB
YAML
121 lines
3.7 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/qcom,sm8250-pinctrl.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Technologies, Inc. SM8250 TLMM block
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maintainers:
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- Bjorn Andersson <bjorn.andersson@linaro.org>
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description:
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Top Level Mode Multiplexer pin controller in the Qualcomm SM8250 SoC.
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properties:
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compatible:
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const: qcom,sm8250-pinctrl
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reg:
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maxItems: 3
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reg-names:
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items:
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- const: west
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- const: south
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- const: north
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interrupts:
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maxItems: 1
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gpio-reserved-ranges:
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minItems: 1
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maxItems: 90
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gpio-line-names:
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maxItems: 180
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patternProperties:
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"-state$":
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oneOf:
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- $ref: "#/$defs/qcom-sm8250-tlmm-state"
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- patternProperties:
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"-pins$":
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$ref: "#/$defs/qcom-sm8250-tlmm-state"
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additionalProperties: false
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$defs:
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qcom-sm8250-tlmm-state:
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type: object
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description:
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Pinctrl node's client devices use subnodes for desired pin configuration.
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Client device subnodes use below standard properties.
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$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
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unevaluatedProperties: false
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properties:
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pins:
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description:
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List of gpio pins affected by the properties specified in this
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subnode.
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items:
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oneOf:
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- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9])$"
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- enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ]
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minItems: 1
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maxItems: 36
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function:
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description:
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Specify the alternative function to be configured for the specified
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pins.
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enum: [ aoss_cti, atest, audio_ref, cam_mclk, cci_async, cci_i2c,
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cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4, cri_trng,
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cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1,
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ddr_pxi2, ddr_pxi3, dp_hot, dp_lcd, gcc_gp1, gcc_gp2, gcc_gp3, gpio,
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ibi_i3c, jitter_bist, lpass_slimbus, mdp_vsync, mdp_vsync0,
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mdp_vsync1, mdp_vsync2, mdp_vsync3, mi2s0_data0, mi2s0_data1,
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mi2s0_sck, mi2s0_ws, mi2s1_data0, mi2s1_data1, mi2s1_sck, mi2s1_ws,
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mi2s2_data0, mi2s2_data1, mi2s2_sck, mi2s2_ws, pci_e0, pci_e1,
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pci_e2, phase_flag, pll_bist, pll_bypassnl, pll_clk, pll_reset,
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pri_mi2s, prng_rosc, qdss_cti, qdss_gpio, qspi0, qspi1, qspi2, qspi3,
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qspi_clk, qspi_cs, qup0, qup1, qup10, qup11, qup12, qup13, qup14,
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qup15, qup16, qup17, qup18, qup19, qup2, qup3, qup4, qup5, qup6,
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qup7, qup8, qup9, qup_l4, qup_l5, qup_l6, sd_write, sdc40, sdc41,
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sdc42, sdc43, sdc4_clk, sdc4_cmd, sec_mi2s, sp_cmu, tgu_ch0, tgu_ch1,
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tgu_ch2, tgu_ch3, tsense_pwm1, tsense_pwm2, tsif0_clk, tsif0_data,
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tsif0_en, tsif0_error, tsif0_sync, tsif1_clk, tsif1_data, tsif1_en,
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tsif1_error, tsif1_sync, usb2phy_ac, usb_phy, vsense_trigger ]
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required:
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- pins
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allOf:
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- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
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required:
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- compatible
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- reg
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- reg-names
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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pinctrl@1f00000 {
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compatible = "qcom,sm8250-pinctrl";
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reg = <0x0f100000 0x300000>,
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<0x0f500000 0x300000>,
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<0x0f900000 0x300000>;
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reg-names = "west", "south", "north";
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interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-ranges = <&tlmm 0 0 181>; /* GPIOs + ufs_reset */
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wakeup-parent = <&pdc>;
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};
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