145 lines
4.4 KiB
YAML
145 lines
4.4 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/qcom,sc7180-pinctrl.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm SC7180 TLMM pin controller
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maintainers:
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- Bjorn Andersson <andersson@kernel.org>
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- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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description:
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Top Level Mode Multiplexer pin controller in Qualcomm SC7180 SoC.
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properties:
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compatible:
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const: qcom,sc7180-pinctrl
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reg:
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maxItems: 3
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reg-names:
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items:
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- const: west
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- const: north
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- const: south
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interrupts:
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maxItems: 1
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gpio-reserved-ranges:
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minItems: 1
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maxItems: 60
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gpio-line-names:
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maxItems: 119
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patternProperties:
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"-state$":
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oneOf:
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- $ref: "#/$defs/qcom-sc7180-tlmm-state"
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- patternProperties:
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"-pins$":
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$ref: "#/$defs/qcom-sc7180-tlmm-state"
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additionalProperties: false
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$defs:
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qcom-sc7180-tlmm-state:
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type: object
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description:
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Pinctrl node's client devices use subnodes for desired pin configuration.
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Client device subnodes use below standard properties.
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$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
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unevaluatedProperties: false
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properties:
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pins:
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description:
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List of gpio pins affected by the properties specified in this
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subnode.
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items:
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oneOf:
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- pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-8])$"
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- enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk,
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sdc2_cmd, sdc2_data, ufs_reset ]
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minItems: 1
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maxItems: 36
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function:
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description:
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Specify the alternative function to be configured for the specified
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pins.
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enum: [ adsp_ext, agera_pll, aoss_cti, atest_char, atest_char0,
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atest_char1, atest_char2, atest_char3, atest_tsens,
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atest_tsens2, atest_usb1, atest_usb10, atest_usb11,
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atest_usb12, atest_usb13, atest_usb2, atest_usb20, atest_usb21,
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atest_usb22, atest_usb23, audio_ref, btfm_slimbus, cam_mclk,
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cci_async, cci_i2c, cci_timer0, cci_timer1, cci_timer2,
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cci_timer3, cci_timer4, cri_trng, dbg_out, ddr_bist, ddr_pxi0,
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ddr_pxi1, ddr_pxi2, ddr_pxi3, dp_hot, edp_lcd, gcc_gp1,
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gcc_gp2, gcc_gp3, gpio, gp_pdm0, gp_pdm1, gp_pdm2, gps_tx,
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jitter_bist, ldo_en, ldo_update, lpass_ext, mdp_vsync,
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mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, mi2s_0, mi2s_1,
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mi2s_2, mss_lte, m_voc, pa_indicator, phase_flag, PLL_BIST,
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pll_bypassnl, pll_reset, prng_rosc, qdss, qdss_cti,
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qlink_enable, qlink_request, qspi_clk, qspi_cs, qspi_data,
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qup00, qup01, qup02_i2c, qup02_uart, qup03, qup04_i2c,
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qup04_uart, qup05, qup10, qup11_i2c, qup11_uart, qup12,
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qup13_i2c, qup13_uart, qup14, qup15, sdc1_tb, sdc2_tb,
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sd_write, sp_cmu, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3,
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tsense_pwm1, tsense_pwm2, uim1, uim2, uim_batt, usb_phy, vfr_1,
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_V_GPIO, _V_PPS_IN, _V_PPS_OUT, vsense_trigger, wlan1_adc0,
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wlan1_adc1, wlan2_adc0, wlan2_adc1 ]
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required:
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- pins
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allOf:
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- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
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required:
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- compatible
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- reg
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- reg-names
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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tlmm: pinctrl@3500000 {
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compatible = "qcom,sc7180-pinctrl";
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reg = <0x03500000 0x300000>,
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<0x03900000 0x300000>,
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<0x03d00000 0x300000>;
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reg-names = "west", "north", "south";
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interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-ranges = <&tlmm 0 0 120>;
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wakeup-parent = <&pdc>;
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dp_hot_plug_det: dp-hot-plug-det-state {
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pins = "gpio117";
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function = "dp_hot";
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};
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qup_spi11_cs_gpio: qup-spi11-cs-gpio-state {
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spi-pins {
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pins = "gpio53", "gpio54", "gpio55";
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function = "qup15";
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};
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cs-pins {
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pins = "gpio56";
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function = "gpio";
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};
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};
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};
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