111 lines
4.1 KiB
YAML
111 lines
4.1 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra20-pinmux.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NVIDIA Tegra20 Pinmux Controller
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maintainers:
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- Thierry Reding <thierry.reding@gmail.com>
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- Jon Hunter <jonathanh@nvidia.com>
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properties:
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compatible:
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const: nvidia,tegra20-pinmux
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reg:
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items:
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- description: tri-state registers
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- description: mux register
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- description: pull-up/down registers
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- description: pad control registers
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patternProperties:
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"^pinmux(-[a-z0-9-_]+)?$":
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type: object
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# pin groups
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additionalProperties:
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$ref: nvidia,tegra-pinmux-common.yaml
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additionalProperties: false
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properties:
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nvidia,pins:
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items:
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enum: [ ata, atb, atc, atd, ate, cdev1, cdev2, crtp, csus, dap1,
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dap2, dap3, dap4, ddc, dta, dtb, dtc, dtd, dte, dtf, gma,
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gmb, gmc, gmd, gme, gpu, gpu7, gpv, hdint, i2cp, irrx,
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irtx, kbca, kbcb, kbcc, kbcd, kbce, kbcf, lcsn, ld0, ld1,
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ld2, ld3, ld4, ld5, ld6, ld7, ld8, ld9, ld10, ld11, ld12,
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ld13, ld14, ld15, ld16, ld17, ldc, ldi, lhp0, lhp1, lhp2,
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lhs, lm0, lm1, lpp, lpw0, lpw1, lpw2, lsc0, lsc1, lsck,
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lsda, lsdi, lspi, lvp0, lvp1, lvs, owc, pmc, pta, rm, sdb,
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sdc, sdd, sdio1, slxa, slxc, slxd, slxk, spdi, spdo, spia,
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spib, spic, spid, spie, spif, spig, spih, uaa, uab, uac,
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uad, uca, ucb, uda,
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# tristate groups
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ck32, ddrc, pmca, pmcb, pmcc, pmcd, pmce, xm2c, xm2d, ls,
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lc, ld17_0, ld19_18, ld21_20, ld23_22,
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# drive groups
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drive_ao1, drive_ao2, drive_at1, drive_at2, drive_cdev1,
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drive_cdev2, drive_csus, drive_dap1, drive_dap2,
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drive_dap3, drive_dap4, drive_dbg, drive_lcd1, drive_lcd2,
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drive_sdmmc2, drive_sdmmc3, drive_spi, drive_uaa,
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drive_uab, drive_uart2, drive_uart3, drive_vi1, drive_vi2,
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drive_xm2a, drive_xm2c, drive_xm2d, drive_xm2clk,
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drive_sdio1, drive_crt, drive_ddc, drive_gma, drive_gmb,
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drive_gmc, drive_gmd, drive_gme, drive_owr, drive_uda ]
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nvidia,function:
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enum: [ ahb_clk, apb_clk, audio_sync, crt, dap1, dap2, dap3, dap4,
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dap5, displaya, displayb, emc_test0_dll, emc_test1_dll, gmi,
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gmi_int, hdmi, i2cp, i2c1, i2c2, i2c3, ide, irda, kbc, mio,
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mipi_hs, nand, osc, owr, pcie, plla_out, pllc_out1,
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pllm_out1, pllp_out2, pllp_out3, pllp_out4, pwm, pwr_intr,
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pwr_on, rsvd1, rsvd2, rsvd3, rsvd4, rtck, sdio1, sdio2,
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sdio3, sdio4, sflash, spdif, spi1, spi2, spi2_alt, spi3,
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spi4, trace, twc, uarta, uartb, uartc, uartd, uarte, ulpi,
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vi, vi_sensor_clk, xio ]
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nvidia,pull: true
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nvidia,tristate: true
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nvidia,schmitt: true
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nvidia,pull-down-strength: true
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nvidia,pull-up-strength: true
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nvidia,high-speed-mode: true
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nvidia,low-power-mode: true
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nvidia,slew-rate-rising: true
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nvidia,slew-rate-falling: true
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required:
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- nvidia,pins
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additionalProperties: false
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required:
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- compatible
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- reg
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examples:
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- |
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#include <dt-bindings/clock/tegra20-car.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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pinctrl@70000000 {
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compatible = "nvidia,tegra20-pinmux";
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reg = <0x70000014 0x10>, /* Tri-state registers */
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<0x70000080 0x20>, /* Mux registers */
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<0x700000a0 0x14>, /* Pull-up/down registers */
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<0x70000868 0xa8>; /* Pad control registers */
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pinmux {
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atb {
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nvidia,pins = "atb", "gma", "gme";
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nvidia,function = "sdio4";
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nvidia,pull = <0>;
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nvidia,tristate = <0>;
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};
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};
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};
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...
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