159 lines
5.6 KiB
Plaintext
159 lines
5.6 KiB
Plaintext
Lantiq XWAY pinmux controller
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Required properties:
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- compatible: "lantiq,<chip>-pinctrl", where <chip> is:
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"ase" (XWAY AMAZON Family)
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"danube" (XWAY DANUBE Family)
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"xrx100" (XWAY xRX100 Family)
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"xrx200" (XWAY xRX200 Family)
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"xrx300" (XWAY xRX300 Family)
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- reg: Should contain the physical address and length of the gpio/pinmux
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register range
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Please refer to pinctrl-bindings.txt in this directory for details of the
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common pinctrl bindings used by client devices, including the meaning of the
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phrase "pin configuration node".
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Lantiq's pin configuration nodes act as a container for an arbitrary number of
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subnodes. Each of these subnodes represents some desired configuration for a
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pin, a group, or a list of pins or groups. This configuration can include the
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mux function to select on those group(s), and two pin configuration parameters:
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pull-up and open-drain
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The name of each subnode is not important as long as it is unique; all subnodes
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should be enumerated and processed purely based on their content.
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Each subnode only affects those parameters that are explicitly listed. In
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other words, a subnode that lists a mux function but no pin configuration
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parameters implies no information about any pin configuration parameters.
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Similarly, a pin subnode that describes a pullup parameter implies no
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information about e.g. the mux function.
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We support 2 types of nodes.
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Definition of mux function groups:
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Required subnode-properties:
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- lantiq,groups : An array of strings. Each string contains the name of a group.
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Valid values for these names are listed below.
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- lantiq,function: A string containing the name of the function to mux to the
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group. Valid values for function names are listed below.
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Valid values for group and function names:
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AMAZON:
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mux groups:
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exin0, exin1, exin2, jtag, spi_di, spi_do, spi_clk, spi_cs1, spi_cs2,
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spi_cs3, spi_cs4, spi_cs5, spi_cs6, asc, stp, gpt1, gpt2, gpt3, clkout0,
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clkout1, clkout2, mdio, dfe led0, dfe led1, ephy led0, ephy led1, ephy led2
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functions:
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spi, asc, cgu, jtag, exin, stp, gpt, mdio, ephy, dfe
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DANUBE:
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mux groups:
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exin0, exin1, exin2, jtag, ebu a23, ebu a24, ebu a25, ebu clk, ebu cs1,
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ebu wait, nand ale, nand cs1, nand cle, spi_di, spi_do, spi_clk, spi_cs1,
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spi_cs2, spi_cs3, spi_cs4, spi_cs5, spi_cs6, asc0, asc0 cts rts, stp, nmi,
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gpt1, gpt2, gpt3, clkout0, clkout1, clkout2, clkout3, gnt1, gnt2, gnt3,
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req1, req2, req3, dfe led0, dfe led1
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functions:
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spi, asc, cgu, jtag, exin, stp, gpt, nmi, pci, ebu, dfe
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xRX100:
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mux groups:
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exin0, exin1, exin2, exin3, exin4, ebu a23, ebu a24, ebu a25, ebu clk,
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ebu cs1, ebu wait, nand ale, nand cs1, nand cle, nand rdy, nand rd,
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spi_di, spi_do, spi_clk, spi_cs1, spi_cs2, spi_cs3, spi_cs4, spi_cs5,
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spi_cs6, asc0, asc0 cts rts, stp, nmi, gpt1, gpt2, gpt3, clkout0, clkout1,
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clkout2, clkout3, gnt1, gnt2, gnt3, gnt4, req1, req2, req3, req4, mdio,
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dfe led0, dfe led1
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functions:
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spi, asc, cgu, exin, stp, gpt, nmi, pci, ebu, mdio, dfe
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xRX200:
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mux groups:
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exin0, exin1, exin2, exin3, exin4, ebu a23, ebu a24, ebu a25, ebu clk,
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ebu cs1, ebu wait, nand ale, nand cs1, nand cle, nand rdy, nand rd,
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spi_di, spi_do, spi_clk, spi_cs1, spi_cs2, spi_cs3, spi_cs4, spi_cs5,
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spi_cs6, usif uart_rx, usif uart_tx, usif uart_rts, usif uart_cts,
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usif uart_dtr, usif uart_dsr, usif uart_dcd, usif uart_ri, usif spi_di,
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usif spi_do, usif spi_clk, usif spi_cs0, usif spi_cs1, usif spi_cs2,
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stp, nmi, gpt1, gpt2, gpt3, clkout0, clkout1, clkout2, clkout3, gnt1,
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gnt2, gnt3, gnt4, req1, req2, req3, req4, mdio, dfe led0, dfe led1,
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gphy0 led0, gphy0 led1, gphy0 led2, gphy1 led0, gphy1 led1, gphy1 led2
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functions:
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spi, usif, cgu, exin, stp, gpt, nmi, pci, ebu, mdio, dfe, gphy
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xRX300:
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mux groups:
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exin0, exin1, exin2, exin4, nand ale, nand cs0, nand cs1, nand cle,
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nand rdy, nand rd, nand_d0, nand_d1, nand_d2, nand_d3, nand_d4, nand_d5,
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nand_d6, nand_d7, nand_d1, nand wr, nand wp, nand se, spi_di, spi_do,
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spi_clk, spi_cs1, spi_cs4, spi_cs6, usif uart_rx, usif uart_tx,
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usif spi_di, usif spi_do, usif spi_clk, usif spi_cs0, stp, clkout2,
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mdio, dfe led0, dfe led1, ephy0 led0, ephy0 led1, ephy1 led0, ephy1 led1
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functions:
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spi, usif, cgu, exin, stp, ebu, mdio, dfe, ephy
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Definition of pin configurations:
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Required subnode-properties:
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- lantiq,pins : An array of strings. Each string contains the name of a pin.
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Valid values for these names are listed below.
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Optional subnode-properties:
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- lantiq,pull: Integer, representing the pull-down/up to apply to the pin.
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0: none, 1: down, 2: up.
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- lantiq,open-drain: Boolean, enables open-drain on the defined pin.
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Valid values for AMAZON pin names:
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Pinconf pins can be referenced via the names io0-io31.
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Valid values for DANUBE pin names:
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Pinconf pins can be referenced via the names io0-io31.
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Valid values for xRX100 pin names:
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Pinconf pins can be referenced via the names io0-io55.
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Valid values for xRX200 pin names:
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Pinconf pins can be referenced via the names io0-io49.
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Valid values for xRX300 pin names:
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Pinconf pins can be referenced via the names io0-io1,io3-io6,io8-io11,
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io13-io19,io23-io27,io34-io36,
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io42-io43,io48-io61.
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Example:
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gpio: pinmux@e100b10 {
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compatible = "lantiq,danube-pinctrl";
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pinctrl-names = "default";
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pinctrl-0 = <&state_default>;
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#gpio-cells = <2>;
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gpio-controller;
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reg = <0xE100B10 0xA0>;
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state_default: pinmux {
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stp {
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lantiq,groups = "stp";
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lantiq,function = "stp";
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};
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pci {
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lantiq,groups = "gnt1";
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lantiq,function = "pci";
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};
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conf_out {
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lantiq,pins = "io4", "io5", "io6"; /* stp */
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lantiq,open-drain;
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lantiq,pull = <0>;
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};
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};
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};
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