75 lines
2.1 KiB
YAML
75 lines
2.1 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
|
%YAML 1.2
|
|
---
|
|
$id: http://devicetree.org/schemas/pinctrl/fsl,scu-pinctrl.yaml#
|
|
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
|
|
|
title: i.MX SCU Client Device Node - Pinctrl Based on SCU Message Protocol
|
|
|
|
maintainers:
|
|
- Dong Aisheng <aisheng.dong@nxp.com>
|
|
|
|
description: i.MX SCU Client Device Node
|
|
Client nodes are maintained as children of the relevant IMX-SCU device node.
|
|
This binding uses the i.MX common pinctrl binding.
|
|
(Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt)
|
|
|
|
allOf:
|
|
- $ref: pinctrl.yaml#
|
|
|
|
properties:
|
|
compatible:
|
|
enum:
|
|
- fsl,imx8qm-iomuxc
|
|
- fsl,imx8qxp-iomuxc
|
|
- fsl,imx8dxl-iomuxc
|
|
|
|
patternProperties:
|
|
'grp$':
|
|
type: object
|
|
description:
|
|
Pinctrl node's client devices use subnodes for desired pin configuration.
|
|
Client device subnodes use below standard properties.
|
|
|
|
properties:
|
|
fsl,pins:
|
|
description:
|
|
each entry consists of 3 integers and represents the pin ID, the mux value
|
|
and pad setting for the pin. The first 2 integers - pin_id and mux_val - are
|
|
specified using a PIN_FUNC_ID macro, which can be found in
|
|
<include/dt-bindings/pinctrl/pads-imx8qxp.h>. The last integer is
|
|
the pad setting value like pull-up on this pin. Please refer to the
|
|
appropriate i.MX8 Reference Manual for detailed pad CONFIG settings.
|
|
$ref: /schemas/types.yaml#/definitions/uint32-matrix
|
|
items:
|
|
items:
|
|
- description: |
|
|
"pin_id" indicates the pin ID
|
|
- description: |
|
|
"mux_val" indicates the mux value to be applied.
|
|
- description: |
|
|
"pad_setting" indicates the pad configuration value to be applied.
|
|
|
|
required:
|
|
- fsl,pins
|
|
|
|
additionalProperties: false
|
|
|
|
required:
|
|
- compatible
|
|
|
|
additionalProperties: false
|
|
|
|
examples:
|
|
- |
|
|
pinctrl {
|
|
compatible = "fsl,imx8qxp-iomuxc";
|
|
|
|
pinctrl_lpuart0: lpuart0grp {
|
|
fsl,pins = <
|
|
111 0 0x06000020
|
|
112 0 0x06000020
|
|
>;
|
|
};
|
|
};
|