91 lines
2.5 KiB
YAML
91 lines
2.5 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/fsl,imx8m-pinctrl.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Freescale IMX8M IOMUX Controller
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maintainers:
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- Peng Fan <peng.fan@nxp.com>
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description:
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Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
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for common binding part and usage.
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properties:
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compatible:
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enum:
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- fsl,imx8mm-iomuxc
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- fsl,imx8mn-iomuxc
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- fsl,imx8mp-iomuxc
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- fsl,imx8mq-iomuxc
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reg:
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maxItems: 1
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# Client device subnode's properties
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patternProperties:
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'grp$':
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type: object
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description:
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Pinctrl node's client devices use subnodes for desired pin configuration.
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Client device subnodes use below standard properties.
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properties:
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fsl,pins:
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description:
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each entry consists of 6 integers and represents the mux and config
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setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
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mux_val input_val> are specified using a PIN_FUNC_ID macro, which can
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be found in <arch/arm64/boot/dts/freescale/imx8m[m,n,p,q]-pinfunc.h>.
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The last integer CONFIG is the pad setting value like pull-up on this
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pin. Please refer to i.MX8M Mini/Nano/Plus/Quad Reference Manual for
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detailed CONFIG settings.
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$ref: /schemas/types.yaml#/definitions/uint32-matrix
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items:
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items:
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- description: |
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"mux_reg" indicates the offset of mux register.
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- description: |
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"conf_reg" indicates the offset of pad configuration register.
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- description: |
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"input_reg" indicates the offset of select input register.
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- description: |
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"mux_val" indicates the mux value to be applied.
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- description: |
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"input_val" indicates the select input value to be applied.
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- description: |
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"pad_setting" indicates the pad configuration value to be
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applied.
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required:
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- fsl,pins
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additionalProperties: false
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allOf:
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- $ref: pinctrl.yaml#
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required:
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- compatible
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- reg
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additionalProperties: false
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examples:
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# Pinmux controller node
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- |
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iomuxc: pinctrl@30330000 {
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compatible = "fsl,imx8mm-iomuxc";
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reg = <0x30330000 0x10000>;
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pinctrl_uart2: uart2grp {
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fsl,pins =
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<0x23C 0x4A4 0x4FC 0x0 0x0 0x140>,
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<0x240 0x4A8 0x000 0x0 0x0 0x140>;
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};
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};
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...
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