115 lines
2.8 KiB
YAML
115 lines
2.8 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/xlnx,xdma-host.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Xilinx XDMA PL PCIe Root Port Bridge
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maintainers:
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- Thippeswamy Havalige <thippeswamy.havalige@amd.com>
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allOf:
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- $ref: /schemas/pci/pci-bus.yaml#
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properties:
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compatible:
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const: xlnx,xdma-host-3.00
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reg:
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maxItems: 1
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ranges:
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maxItems: 2
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interrupts:
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items:
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- description: interrupt asserted when miscellaneous interrupt is received.
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- description: msi0 interrupt asserted when an MSI is received.
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- description: msi1 interrupt asserted when an MSI is received.
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interrupt-names:
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items:
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- const: misc
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- const: msi0
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- const: msi1
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interrupt-map-mask:
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items:
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- const: 0
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- const: 0
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- const: 0
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- const: 7
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interrupt-map:
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maxItems: 4
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"#interrupt-cells":
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const: 1
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interrupt-controller:
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description: identifies the node as an interrupt controller
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type: object
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properties:
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interrupt-controller: true
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"#address-cells":
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const: 0
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"#interrupt-cells":
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const: 1
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required:
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- interrupt-controller
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- "#address-cells"
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- "#interrupt-cells"
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additionalProperties: false
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required:
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- compatible
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- reg
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- ranges
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- interrupts
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- interrupt-map
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- interrupt-map-mask
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- "#interrupt-cells"
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- interrupt-controller
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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pcie@a0000000 {
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compatible = "xlnx,xdma-host-3.00";
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reg = <0x0 0xa0000000 0x0 0x10000000>;
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ranges = <0x2000000 0x0 0xb0000000 0x0 0xb0000000 0x0 0x1000000>,
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<0x43000000 0x5 0x0 0x5 0x0 0x0 0x1000000>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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device_type = "pci";
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "misc", "msi0", "msi1";
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interrupt-map-mask = <0x0 0x0 0x0 0x7>;
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interrupt-map = <0 0 0 1 &pcie_intc_0 0>,
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<0 0 0 2 &pcie_intc_0 1>,
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<0 0 0 3 &pcie_intc_0 2>,
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<0 0 0 4 &pcie_intc_0 3>;
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pcie_intc_0: interrupt-controller {
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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};
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};
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};
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