243 lines
5.7 KiB
YAML
243 lines
5.7 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/mediatek-pcie-gen3.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Gen3 PCIe controller on MediaTek SoCs
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maintainers:
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- Jianjun Wang <jianjun.wang@mediatek.com>
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description: |+
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PCIe Gen3 MAC controller for MediaTek SoCs, it supports Gen3 speed
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and compatible with Gen2, Gen1 speed.
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This PCIe controller supports up to 256 MSI vectors, the MSI hardware
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block diagram is as follows:
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+-----+
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| GIC |
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+-----+
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^
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port->irq
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+-+-+-+-+-+-+-+-+
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|0|1|2|3|4|5|6|7| (PCIe intc)
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+-+-+-+-+-+-+-+-+
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^ ^ ^
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| | ... |
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+-------+ +------+ +-----------+
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| | |
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+-+-+---+--+--+ +-+-+---+--+--+ +-+-+---+--+--+
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|0|1|...|30|31| |0|1|...|30|31| |0|1|...|30|31| (MSI sets)
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+-+-+---+--+--+ +-+-+---+--+--+ +-+-+---+--+--+
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^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^
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| | | | | | | | | | | | (MSI vectors)
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| | | | | | | | | | | |
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(MSI SET0) (MSI SET1) ... (MSI SET7)
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With 256 MSI vectors supported, the MSI vectors are composed of 8 sets,
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each set has its own address for MSI message, and supports 32 MSI vectors
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to generate interrupt.
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properties:
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compatible:
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oneOf:
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- items:
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- enum:
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- mediatek,mt7986-pcie
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- mediatek,mt8188-pcie
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- mediatek,mt8195-pcie
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- const: mediatek,mt8192-pcie
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- const: mediatek,mt8192-pcie
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reg:
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maxItems: 1
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reg-names:
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items:
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- const: pcie-mac
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interrupts:
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maxItems: 1
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ranges:
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minItems: 1
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maxItems: 8
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iommu-map:
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maxItems: 1
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iommu-map-mask:
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const: 0
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resets:
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minItems: 1
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maxItems: 2
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reset-names:
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minItems: 1
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maxItems: 2
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items:
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enum: [ phy, mac ]
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clocks:
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minItems: 4
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maxItems: 6
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clock-names:
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minItems: 4
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maxItems: 6
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assigned-clocks:
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maxItems: 1
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assigned-clock-parents:
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maxItems: 1
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phys:
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maxItems: 1
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phy-names:
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items:
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- const: pcie-phy
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power-domains:
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maxItems: 1
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'#interrupt-cells':
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const: 1
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interrupt-controller:
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description: Interrupt controller node for handling legacy PCI interrupts.
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type: object
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properties:
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'#address-cells':
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const: 0
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'#interrupt-cells':
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const: 1
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interrupt-controller: true
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required:
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- '#address-cells'
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- '#interrupt-cells'
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- interrupt-controller
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additionalProperties: false
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required:
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- compatible
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- reg
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- reg-names
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- interrupts
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- ranges
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- clocks
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- clock-names
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- '#interrupt-cells'
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- interrupt-controller
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allOf:
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- $ref: /schemas/pci/pci-bus.yaml#
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- if:
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properties:
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compatible:
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const: mediatek,mt8192-pcie
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then:
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properties:
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clock-names:
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items:
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- const: pl_250m
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- const: tl_26m
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- const: tl_96m
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- const: tl_32k
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- const: peri_26m
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- const: top_133m
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- if:
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properties:
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compatible:
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contains:
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enum:
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- mediatek,mt8188-pcie
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- mediatek,mt8195-pcie
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then:
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properties:
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clock-names:
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items:
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- const: pl_250m
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- const: tl_26m
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- const: tl_96m
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- const: tl_32k
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- const: peri_26m
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- const: peri_mem
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- if:
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properties:
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compatible:
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contains:
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enum:
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- mediatek,mt7986-pcie
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then:
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properties:
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clock-names:
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items:
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- const: pl_250m
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- const: tl_26m
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- const: peri_26m
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- const: top_133m
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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bus {
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#address-cells = <2>;
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#size-cells = <2>;
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pcie: pcie@11230000 {
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compatible = "mediatek,mt8192-pcie";
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device_type = "pci";
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#address-cells = <3>;
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#size-cells = <2>;
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reg = <0x00 0x11230000 0x00 0x4000>;
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reg-names = "pcie-mac";
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interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>;
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bus-range = <0x00 0xff>;
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ranges = <0x82000000 0x00 0x12000000 0x00
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0x12000000 0x00 0x1000000>;
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clocks = <&infracfg 44>,
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<&infracfg 40>,
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<&infracfg 43>,
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<&infracfg 97>,
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<&infracfg 99>,
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<&infracfg 111>;
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clock-names = "pl_250m", "tl_26m", "tl_96m",
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"tl_32k", "peri_26m", "top_133m";
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assigned-clocks = <&topckgen 50>;
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assigned-clock-parents = <&topckgen 91>;
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phys = <&pciephy>;
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phy-names = "pcie-phy";
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resets = <&infracfg_rst 2>,
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<&infracfg_rst 3>;
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reset-names = "phy", "mac";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &pcie_intc 0>,
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<0 0 0 2 &pcie_intc 1>,
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<0 0 0 3 &pcie_intc 2>,
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<0 0 0 4 &pcie_intc 3>;
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pcie_intc: interrupt-controller {
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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};
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};
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};
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