146 lines
3.8 KiB
YAML
146 lines
3.8 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/mediatek,mt7621-pcie.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MediaTek MT7621 PCIe controller
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maintainers:
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- Sergio Paracuellos <sergio.paracuellos@gmail.com>
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description: |+
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MediaTek MT7621 PCIe subsys supports a single Root Complex (RC)
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with 3 Root Ports. Each Root Port supports a Gen1 1-lane Link
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allOf:
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- $ref: /schemas/pci/pci-bus.yaml#
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properties:
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compatible:
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const: mediatek,mt7621-pci
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reg:
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items:
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- description: host-pci bridge registers
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- description: pcie port 0 RC control registers
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- description: pcie port 1 RC control registers
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- description: pcie port 2 RC control registers
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ranges:
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maxItems: 2
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patternProperties:
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'^pcie@[0-2],0$':
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type: object
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$ref: /schemas/pci/pci-bus.yaml#
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properties:
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resets:
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maxItems: 1
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clocks:
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maxItems: 1
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phys:
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maxItems: 1
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phy-names:
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pattern: '^pcie-phy[0-2]$'
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required:
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- "#interrupt-cells"
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- interrupt-map-mask
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- interrupt-map
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- resets
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- clocks
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- phys
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- phy-names
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- ranges
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unevaluatedProperties: false
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required:
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- compatible
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- reg
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- ranges
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- "#interrupt-cells"
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- interrupt-map-mask
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- interrupt-map
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- reset-gpios
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/mips-gic.h>
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pcie: pcie@1e140000 {
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compatible = "mediatek,mt7621-pci";
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reg = <0x1e140000 0x100>,
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<0x1e142000 0x100>,
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<0x1e143000 0x100>,
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<0x1e144000 0x100>;
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#address-cells = <3>;
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#size-cells = <2>;
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pinctrl-names = "default";
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pinctrl-0 = <&pcie_pins>;
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device_type = "pci";
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ranges = <0x02000000 0 0x60000000 0x60000000 0 0x10000000>, /* pci memory */
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<0x01000000 0 0x1e160000 0x1e160000 0 0x00010000>; /* io space */
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#interrupt-cells = <1>;
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interrupt-map-mask = <0xF800 0 0 0>;
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interrupt-map = <0x0000 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>,
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<0x0800 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,
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<0x1000 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
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reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
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pcie@0,0 {
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reg = <0x0000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&rstctrl 24>;
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clocks = <&clkctrl 24>;
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phys = <&pcie0_phy 1>;
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phy-names = "pcie-phy0";
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ranges;
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};
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pcie@1,0 {
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reg = <0x0800 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&rstctrl 25>;
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clocks = <&clkctrl 25>;
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phys = <&pcie0_phy 1>;
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phy-names = "pcie-phy1";
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ranges;
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};
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pcie@2,0 {
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reg = <0x1000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&rstctrl 26>;
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clocks = <&clkctrl 26>;
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phys = <&pcie2_phy 0>;
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phy-names = "pcie-phy2";
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ranges;
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};
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};
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...
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