118 lines
2.3 KiB
YAML
118 lines
2.3 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/intel-gw-pcie.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: PCIe RC controller on Intel Gateway SoCs
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maintainers:
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- Rahul Tanwar <rtanwar@maxlinear.com>
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select:
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properties:
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compatible:
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contains:
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const: intel,lgm-pcie
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required:
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- compatible
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allOf:
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- $ref: /schemas/pci/snps,dw-pcie.yaml#
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properties:
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compatible:
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items:
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- const: intel,lgm-pcie
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- const: snps,dw-pcie
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reg:
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items:
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- description: Controller control and status registers.
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- description: PCIe configuration registers.
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- description: Controller application registers.
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reg-names:
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items:
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- const: dbi
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- const: config
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- const: app
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ranges:
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maxItems: 1
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resets:
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maxItems: 1
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clocks:
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maxItems: 1
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phys:
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maxItems: 1
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phy-names:
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const: pcie
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reset-gpios:
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maxItems: 1
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num-lanes:
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maximum: 2
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max-link-speed:
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enum: [1, 2, 3, 4]
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default: 1
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reset-assert-ms:
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description: |
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Delay after asserting reset to the PCIe device.
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maximum: 500
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default: 100
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required:
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- compatible
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- reg
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- reg-names
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- ranges
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- resets
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- clocks
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- phys
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- phy-names
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- reset-gpios
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- '#interrupt-cells'
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- interrupt-map
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- interrupt-map-mask
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/gpio/gpio.h>
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pcie10: pcie@d0e00000 {
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compatible = "intel,lgm-pcie", "snps,dw-pcie";
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device_type = "pci";
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#address-cells = <3>;
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#size-cells = <2>;
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reg = <0xd0e00000 0x1000>,
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<0xd2000000 0x800000>,
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<0xd0a41000 0x1000>;
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reg-names = "dbi", "config", "app";
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linux,pci-domain = <0>;
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max-link-speed = <4>;
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bus-range = <0x00 0x08>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &ioapic1 27 1>,
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<0 0 0 2 &ioapic1 28 1>,
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<0 0 0 3 &ioapic1 29 1>,
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<0 0 0 4 &ioapic1 30 1>;
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ranges = <0x02000000 0 0xd4000000 0xd4000000 0 0x04000000>;
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resets = <&rcu0 0x50 0>;
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clocks = <&cgu0 120>;
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phys = <&cb0phy0>;
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phy-names = "pcie";
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reset-assert-ms = <500>;
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reset-gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
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num-lanes = <2>;
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};
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