174 lines
4.3 KiB
YAML
174 lines
4.3 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/brcm,iproc-pcie.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Broadcom iProc PCIe controller with the platform bus interface
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maintainers:
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- Ray Jui <ray.jui@broadcom.com>
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- Scott Branden <scott.branden@broadcom.com>
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allOf:
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- $ref: /schemas/pci/pci-bus.yaml#
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properties:
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compatible:
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items:
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- enum:
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# for the first generation of PAXB based controller, used in SoCs
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# including NSP, Cygnus, NS2, and Pegasus
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- brcm,iproc-pcie
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# for the second generation of PAXB-based controllers, used in
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# Stingray
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- brcm,iproc-pcie-paxb-v2
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# For the first generation of PAXC based controller, used in NS2
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- brcm,iproc-pcie-paxc
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# For the second generation of PAXC based controller, used in Stingray
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- brcm,iproc-pcie-paxc-v2
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reg:
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maxItems: 1
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description: >
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Base address and length of the PCIe controller I/O register space
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ranges:
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minItems: 1
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maxItems: 2
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description: >
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Ranges for the PCI memory and I/O regions
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phys:
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maxItems: 1
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phy-names:
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items:
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- const: pcie-phy
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dma-coherent: true
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brcm,pcie-ob:
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type: boolean
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description: >
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Some iProc SoCs do not have the outbound address mapping done by the
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ASIC after power on reset. In this case, SW needs to configure it
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brcm,pcie-ob-axi-offset:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: >
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The offset from the AXI address to the internal address used by the
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iProc PCIe core (not the PCIe address)
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msi:
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type: object
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$ref: /schemas/interrupt-controller/msi-controller.yaml#
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unevaluatedProperties: false
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properties:
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compatible:
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items:
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- const: brcm,iproc-msi
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interrupts:
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maxItems: 4
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brcm,pcie-msi-inten:
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type: boolean
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description:
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Needs to be present for some older iProc platforms that require the
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interrupt enable registers to be set explicitly to enable MSI
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msi-parent: true
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dependencies:
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brcm,pcie-ob-axi-offset: ["brcm,pcie-ob"]
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brcm,pcie-msi-inten: [msi-controller]
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required:
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- compatible
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- reg
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- ranges
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if:
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properties:
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compatible:
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contains:
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enum:
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- brcm,iproc-pcie
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then:
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required:
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- interrupt-map
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- interrupt-map-mask
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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gic: interrupt-controller {
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interrupt-controller;
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#interrupt-cells = <3>;
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};
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pcie@18012000 {
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compatible = "brcm,iproc-pcie";
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reg = <0x18012000 0x1000>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_NONE>;
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linux,pci-domain = <0>;
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bus-range = <0x00 0xff>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges = <0x81000000 0 0 0x28000000 0 0x00010000>,
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<0x82000000 0 0x20000000 0x20000000 0 0x04000000>;
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phys = <&phy 0 5>;
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phy-names = "pcie-phy";
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brcm,pcie-ob;
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brcm,pcie-ob-axi-offset = <0x00000000>;
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msi-parent = <&msi0>;
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/* iProc event queue based MSI */
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msi0: msi {
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compatible = "brcm,iproc-msi";
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msi-controller;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 96 IRQ_TYPE_NONE>,
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<GIC_SPI 97 IRQ_TYPE_NONE>,
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<GIC_SPI 98 IRQ_TYPE_NONE>,
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<GIC_SPI 99 IRQ_TYPE_NONE>;
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};
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};
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- |
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pcie@18013000 {
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compatible = "brcm,iproc-pcie";
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reg = <0x18013000 0x1000>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 106 IRQ_TYPE_NONE>;
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linux,pci-domain = <1>;
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bus-range = <0x00 0xff>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges = <0x81000000 0 0 0x48000000 0 0x00010000>,
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<0x82000000 0 0x40000000 0x40000000 0 0x04000000>;
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phys = <&phy 1 6>;
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phy-names = "pcie-phy";
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};
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