58 lines
1.4 KiB
YAML
58 lines
1.4 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/memory-controllers/xlnx,versal-ddrmc-edac.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Xilinx Versal DDRMC (Integrated DDR Memory Controller)
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maintainers:
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- Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
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- Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
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description:
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The integrated DDR Memory Controllers (DDRMCs) support both DDR4 and LPDDR4/
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4X memory interfaces. Versal DDR memory controller has an optional ECC support
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which correct single bit ECC errors and detect double bit ECC errors.
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properties:
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compatible:
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const: xlnx,versal-ddrmc
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reg:
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items:
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- description: DDR Memory Controller registers
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- description: NOC registers corresponding to DDR Memory Controller
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reg-names:
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items:
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- const: base
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- const: noc
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interrupts:
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maxItems: 1
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required:
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- compatible
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- reg
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- reg-names
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- interrupts
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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bus {
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#address-cells = <2>;
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#size-cells = <2>;
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memory-controller@f6150000 {
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compatible = "xlnx,versal-ddrmc";
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reg = <0x0 0xf6150000 0x0 0x2000>, <0x0 0xf6070000 0x0 0x20000>;
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reg-names = "base", "noc";
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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