145 lines
5.7 KiB
YAML
145 lines
5.7 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/memory-controllers/st,stm32-fmc2-ebi-props.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Peripheral properties for ST FMC2 Controller
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maintainers:
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- Christophe Kerello <christophe.kerello@foss.st.com>
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- Marek Vasut <marex@denx.de>
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properties:
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st,fmc2-ebi-cs-transaction-type:
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description: |
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Select one of the transactions type supported
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0: Asynchronous mode 1 SRAM/FRAM.
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1: Asynchronous mode 1 PSRAM.
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2: Asynchronous mode A SRAM/FRAM.
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3: Asynchronous mode A PSRAM.
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4: Asynchronous mode 2 NOR.
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5: Asynchronous mode B NOR.
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6: Asynchronous mode C NOR.
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7: Asynchronous mode D NOR.
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8: Synchronous read synchronous write PSRAM.
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9: Synchronous read asynchronous write PSRAM.
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10: Synchronous read synchronous write NOR.
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11: Synchronous read asynchronous write NOR.
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 0
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maximum: 11
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st,fmc2-ebi-cs-cclk-enable:
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description: Continuous clock enable (first bank must be configured
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in synchronous mode). The FMC_CLK is generated continuously
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during asynchronous and synchronous access. By default, the
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FMC_CLK is only generated during synchronous access.
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$ref: /schemas/types.yaml#/definitions/flag
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st,fmc2-ebi-cs-mux-enable:
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description: Address/Data multiplexed on databus (valid only with
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NOR and PSRAM transactions type). By default, Address/Data
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are not multiplexed.
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$ref: /schemas/types.yaml#/definitions/flag
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st,fmc2-ebi-cs-buswidth:
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description: Data bus width
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [ 8, 16 ]
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default: 16
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st,fmc2-ebi-cs-waitpol-high:
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description: Wait signal polarity (NWAIT signal active high).
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By default, NWAIT is active low.
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$ref: /schemas/types.yaml#/definitions/flag
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st,fmc2-ebi-cs-waitcfg-enable:
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description: The NWAIT signal indicates wheither the data from the
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device are valid or if a wait state must be inserted when accessing
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the device in synchronous mode. By default, the NWAIT signal is
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active one data cycle before wait state.
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$ref: /schemas/types.yaml#/definitions/flag
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st,fmc2-ebi-cs-wait-enable:
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description: The NWAIT signal is enabled (its level is taken into
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account after the programmed latency period to insert wait states
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if asserted). By default, the NWAIT signal is disabled.
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$ref: /schemas/types.yaml#/definitions/flag
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st,fmc2-ebi-cs-asyncwait-enable:
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description: The NWAIT signal is taken into account during asynchronous
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transactions. By default, the NWAIT signal is not taken into account
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during asynchronous transactions.
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$ref: /schemas/types.yaml#/definitions/flag
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st,fmc2-ebi-cs-cpsize:
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description: CRAM page size. The controller splits the burst access
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when the memory page is reached. By default, no burst split when
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crossing page boundary.
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [ 0, 128, 256, 512, 1024 ]
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default: 0
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st,fmc2-ebi-cs-byte-lane-setup-ns:
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description: This property configures the byte lane setup timing
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defined in nanoseconds from NBLx low to Chip Select NEx low.
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st,fmc2-ebi-cs-address-setup-ns:
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description: This property defines the duration of the address setup
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phase in nanoseconds used for asynchronous read/write transactions.
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st,fmc2-ebi-cs-address-hold-ns:
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description: This property defines the duration of the address hold
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phase in nanoseconds used for asynchronous multiplexed read/write
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transactions.
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st,fmc2-ebi-cs-data-setup-ns:
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description: This property defines the duration of the data setup phase
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in nanoseconds used for asynchronous read/write transactions.
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st,fmc2-ebi-cs-bus-turnaround-ns:
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description: This property defines the delay in nanoseconds between the
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end of current read/write transaction and the next transaction.
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st,fmc2-ebi-cs-data-hold-ns:
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description: This property defines the duration of the data hold phase
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in nanoseconds used for asynchronous read/write transactions.
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st,fmc2-ebi-cs-clk-period-ns:
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description: This property defines the FMC_CLK output signal period in
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nanoseconds.
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st,fmc2-ebi-cs-data-latency-ns:
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description: This property defines the data latency before reading or
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writing the first data in nanoseconds.
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st,fmc2-ebi-cs-write-address-setup-ns:
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description: This property defines the duration of the address setup
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phase in nanoseconds used for asynchronous write transactions.
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st,fmc2-ebi-cs-write-address-hold-ns:
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description: This property defines the duration of the address hold
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phase in nanoseconds used for asynchronous multiplexed write
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transactions.
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st,fmc2-ebi-cs-write-data-setup-ns:
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description: This property defines the duration of the data setup
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phase in nanoseconds used for asynchronous write transactions.
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st,fmc2-ebi-cs-write-bus-turnaround-ns:
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description: This property defines the delay between the end of current
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write transaction and the next transaction in nanoseconds.
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st,fmc2-ebi-cs-write-data-hold-ns:
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description: This property defines the duration of the data hold phase
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in nanoseconds used for asynchronous write transactions.
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st,fmc2-ebi-cs-max-low-pulse-ns:
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description: This property defines the maximum chip select low pulse
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duration in nanoseconds for synchronous transactions. When this timing
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reaches 0, the controller splits the current access, toggles NE to
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allow device refresh and restarts a new access.
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additionalProperties: true
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