551 lines
22 KiB
YAML
551 lines
22 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-emc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NVIDIA Tegra124 SoC External Memory Controller
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maintainers:
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- Thierry Reding <thierry.reding@gmail.com>
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- Jon Hunter <jonathanh@nvidia.com>
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description: |
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The EMC interfaces with the off-chip SDRAM to service the request stream
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sent from the memory controller.
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properties:
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compatible:
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const: nvidia,tegra124-emc
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reg:
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maxItems: 1
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clocks:
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items:
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- description: external memory clock
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clock-names:
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items:
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- const: emc
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"#interconnect-cells":
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const: 0
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nvidia,memory-controller:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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phandle of the memory controller node
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power-domains:
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maxItems: 1
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description:
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Phandle of the SoC "core" power domain.
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operating-points-v2:
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description:
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Should contain freqs and voltages and opp-supported-hw property, which
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is a bitfield indicating SoC speedo ID mask.
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patternProperties:
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"^emc-timings-[0-9]+$":
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type: object
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additionalProperties: false
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properties:
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nvidia,ram-code:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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value of the RAM_CODE field in the PMC_STRAPPING_OPT_A register that
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this timing set is used for
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patternProperties:
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"^timing-[0-9]+$":
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type: object
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properties:
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clock-frequency:
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description:
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external memory clock rate in Hz
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minimum: 1000000
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maximum: 1000000000
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nvidia,emc-auto-cal-config:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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value of the EMC_AUTO_CAL_CONFIG register for this set of
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timings
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nvidia,emc-auto-cal-config2:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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value of the EMC_AUTO_CAL_CONFIG2 register for this set of
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timings
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nvidia,emc-auto-cal-config3:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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value of the EMC_AUTO_CAL_CONFIG3 register for this set of
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timings
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nvidia,emc-auto-cal-interval:
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description:
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pad calibration interval in microseconds
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 0
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maximum: 2097151
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nvidia,emc-bgbias-ctl0:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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value of the EMC_BGBIAS_CTL0 register for this set of timings
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nvidia,emc-cfg:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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value of the EMC_CFG register for this set of timings
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nvidia,emc-cfg-2:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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value of the EMC_CFG_2 register for this set of timings
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nvidia,emc-ctt-term-ctrl:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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value of the EMC_CTT_TERM_CTRL register for this set of timings
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nvidia,emc-mode-1:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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value of the EMC_MRW register for this set of timings
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nvidia,emc-mode-2:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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value of the EMC_MRW2 register for this set of timings
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nvidia,emc-mode-4:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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value of the EMC_MRW4 register for this set of timings
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nvidia,emc-mode-reset:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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reset value of the EMC_MRS register for this set of timings
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nvidia,emc-mrs-wait-cnt:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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value of the EMR_MRS_WAIT_CNT register for this set of timings
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nvidia,emc-sel-dpd-ctrl:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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value of the EMC_SEL_DPD_CTRL register for this set of timings
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nvidia,emc-xm2dqspadctrl2:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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value of the EMC_XM2DQSPADCTRL2 register for this set of timings
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nvidia,emc-zcal-cnt-long:
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description:
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number of EMC clocks to wait before issuing any commands after
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clock change
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 0
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maximum: 1023
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nvidia,emc-zcal-interval:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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value of the EMC_ZCAL_INTERVAL register for this set of timings
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nvidia,emc-configuration:
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description:
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EMC timing characterization data. These are the registers (see
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section "15.6.2 EMC Registers" in the TRM) whose values need to
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be specified, according to the board documentation.
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$ref: /schemas/types.yaml#/definitions/uint32-array
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items:
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- description: EMC_RC
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- description: EMC_RFC
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- description: EMC_RFC_SLR
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- description: EMC_RAS
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- description: EMC_RP
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- description: EMC_R2W
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- description: EMC_W2R
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- description: EMC_R2P
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- description: EMC_W2P
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- description: EMC_RD_RCD
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- description: EMC_WR_RCD
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- description: EMC_RRD
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- description: EMC_REXT
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- description: EMC_WEXT
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- description: EMC_WDV
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- description: EMC_WDV_MASK
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- description: EMC_QUSE
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- description: EMC_QUSE_WIDTH
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- description: EMC_IBDLY
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- description: EMC_EINPUT
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- description: EMC_EINPUT_DURATION
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- description: EMC_PUTERM_EXTRA
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- description: EMC_PUTERM_WIDTH
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- description: EMC_PUTERM_ADJ
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- description: EMC_CDB_CNTL_1
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- description: EMC_CDB_CNTL_2
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- description: EMC_CDB_CNTL_3
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- description: EMC_QRST
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- description: EMC_QSAFE
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- description: EMC_RDV
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- description: EMC_RDV_MASK
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- description: EMC_REFRESH
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- description: EMC_BURST_REFRESH_NUM
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- description: EMC_PRE_REFRESH_REQ_CNT
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- description: EMC_PDEX2WR
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- description: EMC_PDEX2RD
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- description: EMC_PCHG2PDEN
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- description: EMC_ACT2PDEN
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- description: EMC_AR2PDEN
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- description: EMC_RW2PDEN
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- description: EMC_TXSR
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- description: EMC_TXSRDLL
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- description: EMC_TCKE
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- description: EMC_TCKESR
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- description: EMC_TPD
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- description: EMC_TFAW
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- description: EMC_TRPAB
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- description: EMC_TCLKSTABLE
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- description: EMC_TCLKSTOP
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- description: EMC_TREFBW
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- description: EMC_FBIO_CFG6
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- description: EMC_ODT_WRITE
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- description: EMC_ODT_READ
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- description: EMC_FBIO_CFG5
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- description: EMC_CFG_DIG_DLL
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- description: EMC_CFG_DIG_DLL_PERIOD
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- description: EMC_DLL_XFORM_DQS0
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- description: EMC_DLL_XFORM_DQS1
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- description: EMC_DLL_XFORM_DQS2
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- description: EMC_DLL_XFORM_DQS3
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- description: EMC_DLL_XFORM_DQS4
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- description: EMC_DLL_XFORM_DQS5
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- description: EMC_DLL_XFORM_DQS6
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- description: EMC_DLL_XFORM_DQS7
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- description: EMC_DLL_XFORM_DQS8
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- description: EMC_DLL_XFORM_DQS9
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- description: EMC_DLL_XFORM_DQS10
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- description: EMC_DLL_XFORM_DQS11
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- description: EMC_DLL_XFORM_DQS12
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- description: EMC_DLL_XFORM_DQS13
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- description: EMC_DLL_XFORM_DQS14
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- description: EMC_DLL_XFORM_DQS15
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- description: EMC_DLL_XFORM_QUSE0
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- description: EMC_DLL_XFORM_QUSE1
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- description: EMC_DLL_XFORM_QUSE2
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- description: EMC_DLL_XFORM_QUSE3
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- description: EMC_DLL_XFORM_QUSE4
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- description: EMC_DLL_XFORM_QUSE5
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- description: EMC_DLL_XFORM_QUSE6
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- description: EMC_DLL_XFORM_QUSE7
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- description: EMC_DLL_XFORM_ADDR0
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- description: EMC_DLL_XFORM_ADDR1
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- description: EMC_DLL_XFORM_ADDR2
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- description: EMC_DLL_XFORM_ADDR3
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- description: EMC_DLL_XFORM_ADDR4
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- description: EMC_DLL_XFORM_ADDR5
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- description: EMC_DLL_XFORM_QUSE8
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- description: EMC_DLL_XFORM_QUSE9
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- description: EMC_DLL_XFORM_QUSE10
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- description: EMC_DLL_XFORM_QUSE11
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- description: EMC_DLL_XFORM_QUSE12
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- description: EMC_DLL_XFORM_QUSE13
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- description: EMC_DLL_XFORM_QUSE14
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- description: EMC_DLL_XFORM_QUSE15
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- description: EMC_DLI_TRIM_TXDQS0
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- description: EMC_DLI_TRIM_TXDQS1
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- description: EMC_DLI_TRIM_TXDQS2
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- description: EMC_DLI_TRIM_TXDQS3
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- description: EMC_DLI_TRIM_TXDQS4
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- description: EMC_DLI_TRIM_TXDQS5
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- description: EMC_DLI_TRIM_TXDQS6
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- description: EMC_DLI_TRIM_TXDQS7
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- description: EMC_DLI_TRIM_TXDQS8
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- description: EMC_DLI_TRIM_TXDQS9
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- description: EMC_DLI_TRIM_TXDQS10
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- description: EMC_DLI_TRIM_TXDQS11
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- description: EMC_DLI_TRIM_TXDQS12
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- description: EMC_DLI_TRIM_TXDQS13
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- description: EMC_DLI_TRIM_TXDQS14
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- description: EMC_DLI_TRIM_TXDQS15
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- description: EMC_DLL_XFORM_DQ0
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- description: EMC_DLL_XFORM_DQ1
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- description: EMC_DLL_XFORM_DQ2
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- description: EMC_DLL_XFORM_DQ3
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- description: EMC_DLL_XFORM_DQ4
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- description: EMC_DLL_XFORM_DQ5
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- description: EMC_DLL_XFORM_DQ6
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- description: EMC_DLL_XFORM_DQ7
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- description: EMC_XM2CMDPADCTRL
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- description: EMC_XM2CMDPADCTRL4
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- description: EMC_XM2CMDPADCTRL5
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- description: EMC_XM2DQPADCTRL2
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- description: EMC_XM2DQPADCTRL3
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- description: EMC_XM2CLKPADCTRL
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- description: EMC_XM2CLKPADCTRL2
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- description: EMC_XM2COMPPADCTRL
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- description: EMC_XM2VTTGENPADCTRL
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- description: EMC_XM2VTTGENPADCTRL2
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- description: EMC_XM2VTTGENPADCTRL3
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- description: EMC_XM2DQSPADCTRL3
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- description: EMC_XM2DQSPADCTRL4
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- description: EMC_XM2DQSPADCTRL5
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- description: EMC_XM2DQSPADCTRL6
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- description: EMC_DSR_VTTGEN_DRV
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- description: EMC_TXDSRVTTGEN
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- description: EMC_FBIO_SPARE
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- description: EMC_ZCAL_WAIT_CNT
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- description: EMC_MRS_WAIT_CNT2
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- description: EMC_CTT
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- description: EMC_CTT_DURATION
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- description: EMC_CFG_PIPE
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- description: EMC_DYN_SELF_REF_CONTROL
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- description: EMC_QPOP
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required:
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- clock-frequency
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- nvidia,emc-auto-cal-config
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- nvidia,emc-auto-cal-config2
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- nvidia,emc-auto-cal-config3
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- nvidia,emc-auto-cal-interval
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- nvidia,emc-bgbias-ctl0
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- nvidia,emc-cfg
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- nvidia,emc-cfg-2
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- nvidia,emc-ctt-term-ctrl
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- nvidia,emc-mode-1
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- nvidia,emc-mode-2
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- nvidia,emc-mode-4
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- nvidia,emc-mode-reset
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- nvidia,emc-mrs-wait-cnt
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- nvidia,emc-sel-dpd-ctrl
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- nvidia,emc-xm2dqspadctrl2
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- nvidia,emc-zcal-cnt-long
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- nvidia,emc-zcal-interval
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- nvidia,emc-configuration
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additionalProperties: false
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- nvidia,memory-controller
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- "#interconnect-cells"
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- operating-points-v2
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/tegra124-car.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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mc: memory-controller@70019000 {
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compatible = "nvidia,tegra124-mc";
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reg = <0x70019000 0x1000>;
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clocks = <&tegra_car TEGRA124_CLK_MC>;
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clock-names = "mc";
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interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
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#iommu-cells = <1>;
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#reset-cells = <1>;
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#interconnect-cells = <1>;
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};
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external-memory-controller@7001b000 {
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compatible = "nvidia,tegra124-emc";
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reg = <0x7001b000 0x1000>;
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clocks = <&car TEGRA124_CLK_EMC>;
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clock-names = "emc";
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nvidia,memory-controller = <&mc>;
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operating-points-v2 = <&dvfs_opp_table>;
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power-domains = <&domain>;
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#interconnect-cells = <0>;
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emc-timings-0 {
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nvidia,ram-code = <3>;
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timing-0 {
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clock-frequency = <12750000>;
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nvidia,emc-auto-cal-config = <0xa1430000>;
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nvidia,emc-auto-cal-config2 = <0x00000000>;
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nvidia,emc-auto-cal-config3 = <0x00000000>;
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nvidia,emc-auto-cal-interval = <0x001fffff>;
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nvidia,emc-bgbias-ctl0 = <0x00000008>;
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nvidia,emc-cfg = <0x73240000>;
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nvidia,emc-cfg-2 = <0x000008c5>;
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nvidia,emc-ctt-term-ctrl = <0x00000802>;
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nvidia,emc-mode-1 = <0x80100003>;
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nvidia,emc-mode-2 = <0x80200008>;
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nvidia,emc-mode-4 = <0x00000000>;
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nvidia,emc-mode-reset = <0x80001221>;
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nvidia,emc-mrs-wait-cnt = <0x000e000e>;
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nvidia,emc-sel-dpd-ctrl = <0x00040128>;
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nvidia,emc-xm2dqspadctrl2 = <0x0130b118>;
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nvidia,emc-zcal-cnt-long = <0x00000042>;
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nvidia,emc-zcal-interval = <0x00000000>;
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nvidia,emc-configuration = <
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0x00000000 /* EMC_RC */
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0x00000003 /* EMC_RFC */
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0x00000000 /* EMC_RFC_SLR */
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0x00000000 /* EMC_RAS */
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0x00000000 /* EMC_RP */
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0x00000004 /* EMC_R2W */
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0x0000000a /* EMC_W2R */
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0x00000003 /* EMC_R2P */
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0x0000000b /* EMC_W2P */
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0x00000000 /* EMC_RD_RCD */
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0x00000000 /* EMC_WR_RCD */
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0x00000003 /* EMC_RRD */
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0x00000003 /* EMC_REXT */
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0x00000000 /* EMC_WEXT */
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0x00000006 /* EMC_WDV */
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0x00000006 /* EMC_WDV_MASK */
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0x00000006 /* EMC_QUSE */
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0x00000002 /* EMC_QUSE_WIDTH */
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0x00000000 /* EMC_IBDLY */
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0x00000005 /* EMC_EINPUT */
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0x00000005 /* EMC_EINPUT_DURATION */
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0x00010000 /* EMC_PUTERM_EXTRA */
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0x00000003 /* EMC_PUTERM_WIDTH */
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0x00000000 /* EMC_PUTERM_ADJ */
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0x00000000 /* EMC_CDB_CNTL_1 */
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0x00000000 /* EMC_CDB_CNTL_2 */
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0x00000000 /* EMC_CDB_CNTL_3 */
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0x00000004 /* EMC_QRST */
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0x0000000c /* EMC_QSAFE */
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0x0000000d /* EMC_RDV */
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0x0000000f /* EMC_RDV_MASK */
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0x00000060 /* EMC_REFRESH */
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0x00000000 /* EMC_BURST_REFRESH_NUM */
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0x00000018 /* EMC_PRE_REFRESH_REQ_CNT */
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0x00000002 /* EMC_PDEX2WR */
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0x00000002 /* EMC_PDEX2RD */
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0x00000001 /* EMC_PCHG2PDEN */
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0x00000000 /* EMC_ACT2PDEN */
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0x00000007 /* EMC_AR2PDEN */
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0x0000000f /* EMC_RW2PDEN */
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0x00000005 /* EMC_TXSR */
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0x00000005 /* EMC_TXSRDLL */
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0x00000004 /* EMC_TCKE */
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0x00000005 /* EMC_TCKESR */
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0x00000004 /* EMC_TPD */
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0x00000000 /* EMC_TFAW */
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0x00000000 /* EMC_TRPAB */
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0x00000005 /* EMC_TCLKSTABLE */
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0x00000005 /* EMC_TCLKSTOP */
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0x00000064 /* EMC_TREFBW */
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0x00000000 /* EMC_FBIO_CFG6 */
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0x00000000 /* EMC_ODT_WRITE */
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0x00000000 /* EMC_ODT_READ */
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0x106aa298 /* EMC_FBIO_CFG5 */
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0x002c00a0 /* EMC_CFG_DIG_DLL */
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0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
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0x00064000 /* EMC_DLL_XFORM_DQS0 */
|
|
0x00064000 /* EMC_DLL_XFORM_DQS1 */
|
|
0x00064000 /* EMC_DLL_XFORM_DQS2 */
|
|
0x00064000 /* EMC_DLL_XFORM_DQS3 */
|
|
0x00064000 /* EMC_DLL_XFORM_DQS4 */
|
|
0x00064000 /* EMC_DLL_XFORM_DQS5 */
|
|
0x00064000 /* EMC_DLL_XFORM_DQS6 */
|
|
0x00064000 /* EMC_DLL_XFORM_DQS7 */
|
|
0x00064000 /* EMC_DLL_XFORM_DQS8 */
|
|
0x00064000 /* EMC_DLL_XFORM_DQS9 */
|
|
0x00064000 /* EMC_DLL_XFORM_DQS10 */
|
|
0x00064000 /* EMC_DLL_XFORM_DQS11 */
|
|
0x00064000 /* EMC_DLL_XFORM_DQS12 */
|
|
0x00064000 /* EMC_DLL_XFORM_DQS13 */
|
|
0x00064000 /* EMC_DLL_XFORM_DQS14 */
|
|
0x00064000 /* EMC_DLL_XFORM_DQS15 */
|
|
0x00000000 /* EMC_DLL_XFORM_QUSE0 */
|
|
0x00000000 /* EMC_DLL_XFORM_QUSE1 */
|
|
0x00000000 /* EMC_DLL_XFORM_QUSE2 */
|
|
0x00000000 /* EMC_DLL_XFORM_QUSE3 */
|
|
0x00000000 /* EMC_DLL_XFORM_QUSE4 */
|
|
0x00000000 /* EMC_DLL_XFORM_QUSE5 */
|
|
0x00000000 /* EMC_DLL_XFORM_QUSE6 */
|
|
0x00000000 /* EMC_DLL_XFORM_QUSE7 */
|
|
0x00000000 /* EMC_DLL_XFORM_ADDR0 */
|
|
0x00000000 /* EMC_DLL_XFORM_ADDR1 */
|
|
0x00000000 /* EMC_DLL_XFORM_ADDR2 */
|
|
0x00000000 /* EMC_DLL_XFORM_ADDR3 */
|
|
0x00000000 /* EMC_DLL_XFORM_ADDR4 */
|
|
0x00000000 /* EMC_DLL_XFORM_ADDR5 */
|
|
0x00000000 /* EMC_DLL_XFORM_QUSE8 */
|
|
0x00000000 /* EMC_DLL_XFORM_QUSE9 */
|
|
0x00000000 /* EMC_DLL_XFORM_QUSE10 */
|
|
0x00000000 /* EMC_DLL_XFORM_QUSE11 */
|
|
0x00000000 /* EMC_DLL_XFORM_QUSE12 */
|
|
0x00000000 /* EMC_DLL_XFORM_QUSE13 */
|
|
0x00000000 /* EMC_DLL_XFORM_QUSE14 */
|
|
0x00000000 /* EMC_DLL_XFORM_QUSE15 */
|
|
0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
|
|
0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
|
|
0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
|
|
0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
|
|
0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
|
|
0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
|
|
0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
|
|
0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
|
|
0x00000000 /* EMC_DLI_TRIM_TXDQS8 */
|
|
0x00000000 /* EMC_DLI_TRIM_TXDQS9 */
|
|
0x00000000 /* EMC_DLI_TRIM_TXDQS10 */
|
|
0x00000000 /* EMC_DLI_TRIM_TXDQS11 */
|
|
0x00000000 /* EMC_DLI_TRIM_TXDQS12 */
|
|
0x00000000 /* EMC_DLI_TRIM_TXDQS13 */
|
|
0x00000000 /* EMC_DLI_TRIM_TXDQS14 */
|
|
0x00000000 /* EMC_DLI_TRIM_TXDQS15 */
|
|
0x000fc000 /* EMC_DLL_XFORM_DQ0 */
|
|
0x000fc000 /* EMC_DLL_XFORM_DQ1 */
|
|
0x000fc000 /* EMC_DLL_XFORM_DQ2 */
|
|
0x000fc000 /* EMC_DLL_XFORM_DQ3 */
|
|
0x0000fc00 /* EMC_DLL_XFORM_DQ4 */
|
|
0x0000fc00 /* EMC_DLL_XFORM_DQ5 */
|
|
0x0000fc00 /* EMC_DLL_XFORM_DQ6 */
|
|
0x0000fc00 /* EMC_DLL_XFORM_DQ7 */
|
|
0x10000280 /* EMC_XM2CMDPADCTRL */
|
|
0x00000000 /* EMC_XM2CMDPADCTRL4 */
|
|
0x00111111 /* EMC_XM2CMDPADCTRL5 */
|
|
0x00000000 /* EMC_XM2DQPADCTRL2 */
|
|
0x00000000 /* EMC_XM2DQPADCTRL3 */
|
|
0x77ffc081 /* EMC_XM2CLKPADCTRL */
|
|
0x00000e0e /* EMC_XM2CLKPADCTRL2 */
|
|
0x81f1f108 /* EMC_XM2COMPPADCTRL */
|
|
0x07070004 /* EMC_XM2VTTGENPADCTRL */
|
|
0x0000003f /* EMC_XM2VTTGENPADCTRL2 */
|
|
0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */
|
|
0x51451400 /* EMC_XM2DQSPADCTRL3 */
|
|
0x00514514 /* EMC_XM2DQSPADCTRL4 */
|
|
0x00514514 /* EMC_XM2DQSPADCTRL5 */
|
|
0x51451400 /* EMC_XM2DQSPADCTRL6 */
|
|
0x0000003f /* EMC_DSR_VTTGEN_DRV */
|
|
0x00000007 /* EMC_TXDSRVTTGEN */
|
|
0x00000000 /* EMC_FBIO_SPARE */
|
|
0x00000042 /* EMC_ZCAL_WAIT_CNT */
|
|
0x000e000e /* EMC_MRS_WAIT_CNT2 */
|
|
0x00000000 /* EMC_CTT */
|
|
0x00000003 /* EMC_CTT_DURATION */
|
|
0x0000f2f3 /* EMC_CFG_PIPE */
|
|
0x800001c5 /* EMC_DYN_SELF_REF_CONTROL */
|
|
0x0000000a /* EMC_QPOP */
|
|
>;
|
|
};
|
|
};
|
|
};
|