129 lines
3.7 KiB
YAML
129 lines
3.7 KiB
YAML
# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/memory-controllers/exynos-srom.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Samsung Exynos SoC SROM Controller driver
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maintainers:
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- Krzysztof Kozlowski <krzk@kernel.org>
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description: |+
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The SROM controller can be used to attach external peripherals. In this case
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extra properties, describing the bus behind it, should be specified.
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properties:
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compatible:
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items:
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- const: samsung,exynos4210-srom
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reg:
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maxItems: 1
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"#address-cells":
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const: 2
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"#size-cells":
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const: 1
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ranges:
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minItems: 1
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maxItems: 4
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description: |
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Reflects the memory layout with four integer values per bank. Format:
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<bank-number> 0 <parent address of bank> <size>
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Up to four banks are supported.
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patternProperties:
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"^.*@[0-3],[a-f0-9]+$":
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type: object
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additionalProperties: true
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description:
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The actual device nodes should be added as subnodes to the SROMc node.
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These subnodes, in addition to regular device specification, should
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contain the following properties, describing configuration
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of the relevant SROM bank.
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properties:
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reg:
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description:
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Bank number, base address (relative to start of the bank) and size
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of the memory mapped for the device. Note that base address will be
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typically 0 as this is the start of the bank.
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maxItems: 1
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reg-io-width:
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enum: [1, 2]
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description:
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Data width in bytes (1 or 2). If omitted, default of 1 is used.
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samsung,srom-page-mode:
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description:
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If page mode is set, 4 data page mode will be configured,
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else normal (1 data) page mode will be set.
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type: boolean
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samsung,srom-timing:
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$ref: /schemas/types.yaml#/definitions/uint32-array
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items:
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minItems: 6
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maxItems: 6
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description: |
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Array of 6 integers, specifying bank timings in the following order:
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Tacp, Tcah, Tcoh, Tacc, Tcos, Tacs.
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Each value is specified in cycles and has the following meaning
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and valid range:
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Tacp: Page mode access cycle at Page mode (0 - 15)
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Tcah: Address holding time after CSn (0 - 15)
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Tcoh: Chip selection hold on OEn (0 - 15)
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Tacc: Access cycle (0 - 31, the actual time is N + 1)
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Tcos: Chip selection set-up before OEn (0 - 15)
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Tacs: Address set-up before CSn (0 - 15)
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required:
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- reg
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- samsung,srom-timing
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required:
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- compatible
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- reg
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additionalProperties: false
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examples:
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- |
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// Example: basic definition, no banks are configured
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memory-controller@12560000 {
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compatible = "samsung,exynos4210-srom";
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reg = <0x12560000 0x14>;
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};
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- |
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// Example: SROMc with SMSC911x ethernet chip on bank 3
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memory-controller@12570000 {
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#address-cells = <2>;
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#size-cells = <1>;
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ranges = <0 0 0x04000000 0x20000 // Bank0
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1 0 0x05000000 0x20000 // Bank1
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2 0 0x06000000 0x20000 // Bank2
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3 0 0x07000000 0x20000>; // Bank3
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compatible = "samsung,exynos4210-srom";
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reg = <0x12570000 0x14>;
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ethernet@3,0 {
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compatible = "smsc,lan9115";
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reg = <3 0 0x10000>; // Bank 3, offset = 0
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phy-mode = "mii";
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interrupt-parent = <&gpx0>;
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interrupts = <5 8>;
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reg-io-width = <2>;
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smsc,irq-push-pull;
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smsc,force-internal-phy;
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samsung,srom-page-mode;
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samsung,srom-timing = <9 12 1 9 1 1>;
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};
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};
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