125 lines
2.9 KiB
YAML
125 lines
2.9 KiB
YAML
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/interconnect/qcom,sm8450-rpmh.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm RPMh Network-On-Chip Interconnect on SM8450
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maintainers:
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- Bjorn Andersson <andersson@kernel.org>
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- Konrad Dybcio <konrad.dybcio@linaro.org>
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description: |
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RPMh interconnect providers support system bandwidth requirements through
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RPMh hardware accelerators known as Bus Clock Manager (BCM).
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See also:: include/dt-bindings/interconnect/qcom,sm8450.h
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properties:
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compatible:
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enum:
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- qcom,sm8450-aggre1-noc
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- qcom,sm8450-aggre2-noc
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- qcom,sm8450-clk-virt
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- qcom,sm8450-config-noc
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- qcom,sm8450-gem-noc
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- qcom,sm8450-lpass-ag-noc
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- qcom,sm8450-mc-virt
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- qcom,sm8450-mmss-noc
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- qcom,sm8450-nsp-noc
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- qcom,sm8450-pcie-anoc
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- qcom,sm8450-system-noc
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reg:
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maxItems: 1
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clocks:
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minItems: 1
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maxItems: 4
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required:
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- compatible
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allOf:
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- $ref: qcom,rpmh-common.yaml#
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,sm8450-clk-virt
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- qcom,sm8450-mc-virt
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then:
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properties:
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reg: false
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else:
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required:
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- reg
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,sm8450-aggre1-noc
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then:
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properties:
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clocks:
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items:
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- description: aggre UFS PHY AXI clock
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- description: aggre USB3 PRIM AXI clock
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,sm8450-aggre2-noc
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then:
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properties:
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clocks:
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items:
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- description: aggre-NOC PCIe 0 AXI clock
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- description: aggre-NOC PCIe 1 AXI clock
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- description: aggre UFS PHY AXI clock
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- description: RPMH CC IPA clock
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- if:
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properties:
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compatible:
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contains:
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enum:
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- qcom,sm8450-aggre1-noc
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- qcom,sm8450-aggre2-noc
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then:
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required:
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- clocks
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else:
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properties:
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clocks: false
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,gcc-sm8450.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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interconnect-0 {
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compatible = "qcom,sm8450-clk-virt";
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#interconnect-cells = <2>;
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qcom,bcm-voters = <&apps_bcm_voter>;
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};
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interconnect@1700000 {
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compatible = "qcom,sm8450-aggre2-noc";
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reg = <0x01700000 0x31080>;
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#interconnect-cells = <2>;
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qcom,bcm-voters = <&apps_bcm_voter>;
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clocks = <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
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<&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,
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<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
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<&rpmhcc RPMH_IPA_CLK>;
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};
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