178 lines
5.1 KiB
YAML
178 lines
5.1 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/iio/resolver/adi,ad2s1210.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Analog Devices AD2S1210 Resolver-to-Digital Converter
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maintainers:
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- Michael Hennerich <michael.hennerich@analog.com>
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description: |
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The AD2S1210 is a complete 10-bit to 16-bit resolution tracking
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resolver-to-digital converter, integrating an on-board programmable
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sinusoidal oscillator that provides sine wave excitation for
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resolvers.
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The AD2S1210 allows the user to read the angular position or the
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angular velocity data directly from the parallel outputs or through
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the serial interface.
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The mode of operation of the communication channel (parallel or serial) is
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selected by the A0 and A1 input pins. In normal mode, data is latched by
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toggling the SAMPLE line and can then be read directly. In configuration mode,
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data is read or written using a register access scheme (address byte with
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read/write flag and data byte).
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A1 A0 Result
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0 0 Normal mode - position output
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0 1 Normal mode - velocity output
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1 0 Reserved
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1 1 Configuration mode
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In normal mode, the resolution of the digital output is selected using
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the RES0 and RES1 input pins. In configuration mode, the resolution is
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selected by setting the RES0 and RES1 bits in the control register.
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RES1 RES0 Resolution (Bits)
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0 0 10
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0 1 12
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1 0 14
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1 1 16
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Note on SPI connections: The CS line on the AD2S1210 should hard-wired to
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logic low and the WR/FSYNC line on the AD2S1210 should be connected to the
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SPI CSn output of the SPI controller.
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Datasheet:
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https://www.analog.com/media/en/technical-documentation/data-sheets/ad2s1210.pdf
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properties:
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compatible:
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const: adi,ad2s1210
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reg:
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maxItems: 1
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spi-max-frequency:
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maximum: 25000000
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spi-cpha: true
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avdd-supply:
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description:
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A 4.75 to 5.25 V regulator that powers the Analog Supply Voltage (AVDD)
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pin.
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dvdd-supply:
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description:
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A 4.75 to 5.25 V regulator that powers the Digital Supply Voltage (DVDD)
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pin.
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vdrive-supply:
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description:
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A 2.3 to 5.25 V regulator that powers the Logic Power Supply Input
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(VDrive) pin.
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clocks:
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maxItems: 1
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description: External oscillator clock (CLKIN).
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reset-gpios:
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description:
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GPIO connected to the /RESET pin. As the line needs to be low for the
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reset to be active, it should be configured as GPIO_ACTIVE_LOW.
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maxItems: 1
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sample-gpios:
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description:
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GPIO connected to the /SAMPLE pin. As the line needs to be low to trigger
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a sample, it should be configured as GPIO_ACTIVE_LOW.
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maxItems: 1
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mode-gpios:
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description:
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GPIO lines connected to the A0 and A1 pins. These pins select the data
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transfer mode.
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minItems: 2
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maxItems: 2
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resolution-gpios:
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description:
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GPIO lines connected to the RES0 and RES1 pins. These pins select the
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resolution of the digital output. If omitted, it is assumed that the
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RES0 and RES1 pins are hard-wired to match the assigned-resolution-bits
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property.
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minItems: 2
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maxItems: 2
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fault-gpios:
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description:
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GPIO lines connected to the LOT and DOS pins. These pins combined indicate
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the type of fault present, if any. As these pins a pulled low to indicate
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a fault condition, they should be configured as GPIO_ACTIVE_LOW.
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minItems: 2
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maxItems: 2
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adi,fixed-mode:
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description:
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This is used to indicate the selected mode if A0 and A1 are hard-wired
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instead of connected to GPIOS (i.e. mode-gpios is omitted).
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$ref: /schemas/types.yaml#/definitions/string
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enum: [config, velocity, position]
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assigned-resolution-bits:
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description:
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Resolution of the digital output required by the application. This
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determines the precision of the angle and/or the maximum speed that can
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be measured. If resolution-gpios is omitted, it is assumed that RES0 and
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RES1 are hard-wired to match this value.
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enum: [10, 12, 14, 16]
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required:
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- compatible
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- reg
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- spi-cpha
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- avdd-supply
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- dvdd-supply
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- vdrive-supply
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- clocks
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- sample-gpios
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- assigned-resolution-bits
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oneOf:
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- required:
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- mode-gpios
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- required:
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- adi,fixed-mode
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allOf:
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- $ref: /schemas/spi/spi-peripheral-props.yaml#
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/gpio/gpio.h>
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spi {
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#address-cells = <1>;
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#size-cells = <0>;
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resolver@0 {
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compatible = "adi,ad2s1210";
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reg = <0>;
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spi-max-frequency = <20000000>;
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spi-cpha;
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avdd-supply = <&avdd_regulator>;
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dvdd-supply = <&dvdd_regulator>;
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vdrive-supply = <&vdrive_regulator>;
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clocks = <&ext_osc>;
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sample-gpios = <&gpio0 90 GPIO_ACTIVE_LOW>;
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mode-gpios = <&gpio0 86 0>, <&gpio0 87 0>;
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resolution-gpios = <&gpio0 88 0>, <&gpio0 89 0>;
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assigned-resolution-bits = <16>;
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};
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};
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