117 lines
3.5 KiB
YAML
117 lines
3.5 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/dma/st,stm32-dma.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: STMicroelectronics STM32 DMA Controller
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description: |
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The STM32 DMA is a general-purpose direct memory access controller capable of
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supporting 8 independent DMA channels. Each channel can have up to 8 requests.
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DMA clients connected to the STM32 DMA controller must use the format
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described in the dma.txt file, using a four-cell specifier for each
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channel: a phandle to the DMA controller plus the following four integer cells:
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1. The channel id
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2. The request line number
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3. A 32bit mask specifying the DMA channel configuration which are device
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dependent:
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-bit 9: Peripheral Increment Address
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0x0: no address increment between transfers
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0x1: increment address between transfers
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-bit 10: Memory Increment Address
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0x0: no address increment between transfers
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0x1: increment address between transfers
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-bit 15: Peripheral Increment Offset Size
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0x0: offset size is linked to the peripheral bus width
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0x1: offset size is fixed to 4 (32-bit alignment)
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-bit 16-17: Priority level
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0x0: low
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0x1: medium
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0x2: high
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0x3: very high
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4. A 32bit bitfield value specifying DMA features which are device dependent:
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-bit 0-1: DMA FIFO threshold selection
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0x0: 1/4 full FIFO
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0x1: 1/2 full FIFO
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0x2: 3/4 full FIFO
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0x3: full FIFO
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-bit 2: DMA direct mode
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0x0: FIFO mode with threshold selectable with bit 0-1
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0x1: Direct mode: each DMA request immediately initiates a transfer
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from/to the memory, FIFO is bypassed.
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-bit 4: alternative DMA request/acknowledge protocol
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0x0: Use standard DMA ACK management, where ACK signal is maintained
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up to the removal of request and transfer completion
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0x1: Use alternative DMA ACK management, where ACK de-assertion does
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not wait for the de-assertion of the REQuest, ACK is only managed
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by transfer completion. This must only be used on channels
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managing transfers for STM32 USART/UART.
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maintainers:
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- Amelie Delaunay <amelie.delaunay@foss.st.com>
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allOf:
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- $ref: dma-controller.yaml#
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properties:
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"#dma-cells":
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const: 4
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compatible:
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const: st,stm32-dma
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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interrupts:
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maxItems: 8
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description: Should contain all of the per-channel DMA
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interrupts in ascending order with respect to the
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DMA channel index.
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resets:
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maxItems: 1
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st,mem2mem:
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$ref: /schemas/types.yaml#/definitions/flag
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description: if defined, it indicates that the controller
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supports memory-to-memory transfer
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required:
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- compatible
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- reg
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- clocks
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- interrupts
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/stm32mp1-clks.h>
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#include <dt-bindings/reset/stm32mp1-resets.h>
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dma-controller@40026400 {
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compatible = "st,stm32-dma";
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reg = <0x40026400 0x400>;
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interrupts = <56>,
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<57>,
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<58>,
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<59>,
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<60>,
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<68>,
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<69>,
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<70>;
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clocks = <&clk_hclk>;
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#dma-cells = <4>;
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st,mem2mem;
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resets = <&rcc 150>;
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dma-requests = <8>;
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};
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...
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