248 lines
7.0 KiB
YAML
248 lines
7.0 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/dma/fsl,edma.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Freescale enhanced Direct Memory Access(eDMA) Controller
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description: |
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The eDMA channels have multiplex capability by programmable
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memory-mapped registers. channels are split into two groups, called
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DMAMUX0 and DMAMUX1, specific DMA request source can only be multiplexed
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by any channel of certain group, DMAMUX0 or DMAMUX1, but not both.
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maintainers:
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- Peng Fan <peng.fan@nxp.com>
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properties:
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compatible:
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oneOf:
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- enum:
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- fsl,vf610-edma
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- fsl,imx7ulp-edma
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- fsl,imx8qm-adma
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- fsl,imx8qm-edma
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- fsl,imx93-edma3
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- fsl,imx93-edma4
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- items:
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- const: fsl,ls1028a-edma
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- const: fsl,vf610-edma
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reg:
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minItems: 1
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maxItems: 3
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interrupts:
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minItems: 1
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maxItems: 64
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interrupt-names:
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minItems: 1
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maxItems: 64
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"#dma-cells":
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enum:
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- 2
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- 3
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dma-channels:
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minItems: 1
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maxItems: 64
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clocks:
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minItems: 1
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maxItems: 2
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clock-names:
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minItems: 1
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maxItems: 2
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big-endian:
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description: |
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If present registers and hardware scatter/gather descriptors of the
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eDMA are implemented in big endian mode, otherwise in little mode.
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type: boolean
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required:
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- "#dma-cells"
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- compatible
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- reg
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- interrupts
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- clocks
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- dma-channels
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allOf:
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- $ref: dma-controller.yaml#
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- if:
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properties:
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compatible:
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contains:
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enum:
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- fsl,imx8qm-adma
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- fsl,imx8qm-edma
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- fsl,imx93-edma3
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- fsl,imx93-edma4
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then:
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properties:
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"#dma-cells":
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const: 3
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# It is not necessary to write the interrupt name for each channel.
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# instead, you can simply maintain the sequential IRQ numbers as
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# defined for the DMA channels.
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interrupt-names: false
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clock-names:
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items:
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- const: dma
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clocks:
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maxItems: 1
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- if:
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properties:
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compatible:
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contains:
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const: fsl,vf610-edma
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then:
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properties:
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clocks:
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minItems: 2
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clock-names:
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items:
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- const: dmamux0
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- const: dmamux1
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interrupts:
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minItems: 2
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maxItems: 2
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interrupt-names:
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items:
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- const: edma-tx
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- const: edma-err
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reg:
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minItems: 2
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maxItems: 3
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"#dma-cells":
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const: 2
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dma-channels:
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const: 32
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- if:
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properties:
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compatible:
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contains:
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const: fsl,imx7ulp-edma
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then:
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properties:
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clock:
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minItems: 2
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clock-names:
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items:
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- const: dma
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- const: dmamux0
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interrupts:
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minItems: 2
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maxItems: 17
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reg:
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minItems: 2
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maxItems: 2
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"#dma-cells":
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const: 2
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dma-channels:
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const: 32
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/vf610-clock.h>
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edma0: dma-controller@40018000 {
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#dma-cells = <2>;
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compatible = "fsl,vf610-edma";
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reg = <0x40018000 0x2000>,
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<0x40024000 0x1000>,
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<0x40025000 0x1000>;
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interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
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<0 9 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "edma-tx", "edma-err";
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dma-channels = <32>;
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clock-names = "dmamux0", "dmamux1";
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clocks = <&clks VF610_CLK_DMAMUX0>, <&clks VF610_CLK_DMAMUX1>;
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};
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/imx7ulp-clock.h>
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edma1: dma-controller@40080000 {
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#dma-cells = <2>;
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compatible = "fsl,imx7ulp-edma";
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reg = <0x40080000 0x2000>,
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<0x40210000 0x1000>;
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dma-channels = <32>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
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/* last is eDMA2-ERR interrupt */
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<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "dma", "dmamux0";
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clocks = <&pcc2 IMX7ULP_CLK_DMA1>, <&pcc2 IMX7ULP_CLK_DMA_MUX1>;
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};
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/imx93-clock.h>
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dma-controller@44000000 {
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compatible = "fsl,imx93-edma3";
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reg = <0x44000000 0x200000>;
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#dma-cells = <3>;
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dma-channels = <31>;
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interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX93_CLK_EDMA1_GATE>;
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clock-names = "dma";
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};
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