154 lines
6.0 KiB
YAML
154 lines
6.0 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/arm/mediatek/mediatek,audsys.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MediaTek AUDSYS controller
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maintainers:
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- Eugen Hristev <eugen.hristev@collabora.com>
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description:
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The MediaTek AUDSYS controller provides various clocks to the system.
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properties:
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compatible:
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oneOf:
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- items:
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- enum:
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- mediatek,mt2701-audsys
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- mediatek,mt6765-audsys
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- mediatek,mt6779-audsys
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- mediatek,mt7622-audsys
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- mediatek,mt8167-audsys
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- mediatek,mt8173-audsys
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- mediatek,mt8183-audsys
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- mediatek,mt8186-audsys
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- mediatek,mt8192-audsys
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- mediatek,mt8516-audsys
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- const: syscon
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- items:
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# Special case for mt7623 for backward compatibility
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- const: mediatek,mt7623-audsys
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- const: mediatek,mt2701-audsys
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- const: syscon
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reg:
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maxItems: 1
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'#clock-cells':
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const: 1
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audio-controller:
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$ref: /schemas/sound/mediatek,mt2701-audio.yaml#
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type: object
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required:
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- compatible
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- '#clock-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/power/mt2701-power.h>
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#include <dt-bindings/clock/mt2701-clk.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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audsys: clock-controller@11220000 {
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compatible = "mediatek,mt7622-audsys", "syscon";
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reg = <0 0x11220000 0 0x2000>;
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#clock-cells = <1>;
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afe: audio-controller {
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compatible = "mediatek,mt2701-audio";
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interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
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interrupt-names = "afe", "asys";
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power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
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clocks = <&infracfg CLK_INFRA_AUDIO>,
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<&topckgen CLK_TOP_AUD_MUX1_SEL>,
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<&topckgen CLK_TOP_AUD_MUX2_SEL>,
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<&topckgen CLK_TOP_AUD_48K_TIMING>,
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<&topckgen CLK_TOP_AUD_44K_TIMING>,
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<&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
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<&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
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<&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
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<&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
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<&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
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<&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
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<&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
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<&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
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<&topckgen CLK_TOP_AUD_I2S1_MCLK>,
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<&topckgen CLK_TOP_AUD_I2S2_MCLK>,
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<&topckgen CLK_TOP_AUD_I2S3_MCLK>,
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<&topckgen CLK_TOP_AUD_I2S4_MCLK>,
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<&audsys CLK_AUD_I2SO1>,
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<&audsys CLK_AUD_I2SO2>,
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<&audsys CLK_AUD_I2SO3>,
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<&audsys CLK_AUD_I2SO4>,
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<&audsys CLK_AUD_I2SIN1>,
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<&audsys CLK_AUD_I2SIN2>,
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<&audsys CLK_AUD_I2SIN3>,
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<&audsys CLK_AUD_I2SIN4>,
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<&audsys CLK_AUD_ASRCO1>,
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<&audsys CLK_AUD_ASRCO2>,
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<&audsys CLK_AUD_ASRCO3>,
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<&audsys CLK_AUD_ASRCO4>,
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<&audsys CLK_AUD_AFE>,
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<&audsys CLK_AUD_AFE_CONN>,
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<&audsys CLK_AUD_A1SYS>,
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<&audsys CLK_AUD_A2SYS>,
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<&audsys CLK_AUD_AFE_MRGIF>;
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clock-names = "infra_sys_audio_clk",
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"top_audio_mux1_sel",
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"top_audio_mux2_sel",
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"top_audio_a1sys_hp",
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"top_audio_a2sys_hp",
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"i2s0_src_sel",
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"i2s1_src_sel",
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"i2s2_src_sel",
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"i2s3_src_sel",
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"i2s0_src_div",
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"i2s1_src_div",
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"i2s2_src_div",
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"i2s3_src_div",
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"i2s0_mclk_en",
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"i2s1_mclk_en",
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"i2s2_mclk_en",
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"i2s3_mclk_en",
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"i2so0_hop_ck",
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"i2so1_hop_ck",
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"i2so2_hop_ck",
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"i2so3_hop_ck",
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"i2si0_hop_ck",
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"i2si1_hop_ck",
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"i2si2_hop_ck",
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"i2si3_hop_ck",
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"asrc0_out_ck",
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"asrc1_out_ck",
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"asrc2_out_ck",
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"asrc3_out_ck",
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"audio_afe_pd",
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"audio_afe_conn_pd",
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"audio_a1sys_pd",
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"audio_a2sys_pd",
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"audio_mrgif_pd";
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assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
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<&topckgen CLK_TOP_AUD_MUX2_SEL>,
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<&topckgen CLK_TOP_AUD_MUX1_DIV>,
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<&topckgen CLK_TOP_AUD_MUX2_DIV>;
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assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
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<&topckgen CLK_TOP_AUD2PLL_90M>;
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assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
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};
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};
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};
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