613 lines
15 KiB
C
613 lines
15 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Universal Flash Storage Host controller driver
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* Copyright (C) 2011-2013 Samsung India Software Operations
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*
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* Authors:
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* Santosh Yaraganavi <santosh.sy@samsung.com>
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* Vinayak Holikatti <h.vinayak@samsung.com>
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*/
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#ifndef _UFSHCI_H
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#define _UFSHCI_H
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#include <linux/types.h>
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#include <ufs/ufs.h>
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enum {
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TASK_REQ_UPIU_SIZE_DWORDS = 8,
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TASK_RSP_UPIU_SIZE_DWORDS = 8,
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ALIGNED_UPIU_SIZE = 512,
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};
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/* UFSHCI Registers */
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enum {
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REG_CONTROLLER_CAPABILITIES = 0x00,
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REG_MCQCAP = 0x04,
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REG_UFS_VERSION = 0x08,
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REG_CONTROLLER_DEV_ID = 0x10,
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REG_CONTROLLER_PROD_ID = 0x14,
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REG_AUTO_HIBERNATE_IDLE_TIMER = 0x18,
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REG_INTERRUPT_STATUS = 0x20,
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REG_INTERRUPT_ENABLE = 0x24,
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REG_CONTROLLER_STATUS = 0x30,
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REG_CONTROLLER_ENABLE = 0x34,
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REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER = 0x38,
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REG_UIC_ERROR_CODE_DATA_LINK_LAYER = 0x3C,
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REG_UIC_ERROR_CODE_NETWORK_LAYER = 0x40,
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REG_UIC_ERROR_CODE_TRANSPORT_LAYER = 0x44,
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REG_UIC_ERROR_CODE_DME = 0x48,
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REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL = 0x4C,
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REG_UTP_TRANSFER_REQ_LIST_BASE_L = 0x50,
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REG_UTP_TRANSFER_REQ_LIST_BASE_H = 0x54,
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REG_UTP_TRANSFER_REQ_DOOR_BELL = 0x58,
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REG_UTP_TRANSFER_REQ_LIST_CLEAR = 0x5C,
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REG_UTP_TRANSFER_REQ_LIST_RUN_STOP = 0x60,
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REG_UTP_TASK_REQ_LIST_BASE_L = 0x70,
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REG_UTP_TASK_REQ_LIST_BASE_H = 0x74,
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REG_UTP_TASK_REQ_DOOR_BELL = 0x78,
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REG_UTP_TASK_REQ_LIST_CLEAR = 0x7C,
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REG_UTP_TASK_REQ_LIST_RUN_STOP = 0x80,
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REG_UIC_COMMAND = 0x90,
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REG_UIC_COMMAND_ARG_1 = 0x94,
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REG_UIC_COMMAND_ARG_2 = 0x98,
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REG_UIC_COMMAND_ARG_3 = 0x9C,
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UFSHCI_REG_SPACE_SIZE = 0xA0,
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REG_UFS_CCAP = 0x100,
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REG_UFS_CRYPTOCAP = 0x104,
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REG_UFS_MEM_CFG = 0x300,
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REG_UFS_MCQ_CFG = 0x380,
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REG_UFS_ESILBA = 0x384,
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REG_UFS_ESIUBA = 0x388,
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UFSHCI_CRYPTO_REG_SPACE_SIZE = 0x400,
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};
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/* Controller capability masks */
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enum {
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MASK_TRANSFER_REQUESTS_SLOTS = 0x0000001F,
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MASK_TASK_MANAGEMENT_REQUEST_SLOTS = 0x00070000,
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MASK_EHSLUTRD_SUPPORTED = 0x00400000,
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MASK_AUTO_HIBERN8_SUPPORT = 0x00800000,
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MASK_64_ADDRESSING_SUPPORT = 0x01000000,
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MASK_OUT_OF_ORDER_DATA_DELIVERY_SUPPORT = 0x02000000,
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MASK_UIC_DME_TEST_MODE_SUPPORT = 0x04000000,
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MASK_CRYPTO_SUPPORT = 0x10000000,
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MASK_MCQ_SUPPORT = 0x40000000,
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};
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/* MCQ capability mask */
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enum {
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MASK_EXT_IID_SUPPORT = 0x00000400,
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};
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enum {
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REG_SQATTR = 0x0,
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REG_SQLBA = 0x4,
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REG_SQUBA = 0x8,
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REG_SQDAO = 0xC,
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REG_SQISAO = 0x10,
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REG_CQATTR = 0x20,
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REG_CQLBA = 0x24,
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REG_CQUBA = 0x28,
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REG_CQDAO = 0x2C,
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REG_CQISAO = 0x30,
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};
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enum {
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REG_SQHP = 0x0,
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REG_SQTP = 0x4,
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REG_SQRTC = 0x8,
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REG_SQCTI = 0xC,
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REG_SQRTS = 0x10,
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};
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enum {
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REG_CQHP = 0x0,
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REG_CQTP = 0x4,
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};
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enum {
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REG_CQIS = 0x0,
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REG_CQIE = 0x4,
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};
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enum {
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SQ_START = 0x0,
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SQ_STOP = 0x1,
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SQ_ICU = 0x2,
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};
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enum {
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SQ_STS = 0x1,
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SQ_CUS = 0x2,
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};
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#define SQ_ICU_ERR_CODE_MASK GENMASK(7, 4)
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#define UFS_MASK(mask, offset) ((mask) << (offset))
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/* UFS Version 08h */
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#define MINOR_VERSION_NUM_MASK UFS_MASK(0xFFFF, 0)
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#define MAJOR_VERSION_NUM_MASK UFS_MASK(0xFFFF, 16)
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#define UFSHCD_NUM_RESERVED 1
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/*
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* Controller UFSHCI version
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* - 2.x and newer use the following scheme:
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* major << 8 + minor << 4
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* - 1.x has been converted to match this in
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* ufshcd_get_ufs_version()
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*/
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static inline u32 ufshci_version(u32 major, u32 minor)
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{
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return (major << 8) + (minor << 4);
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}
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/*
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* HCDDID - Host Controller Identification Descriptor
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* - Device ID and Device Class 10h
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*/
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#define DEVICE_CLASS UFS_MASK(0xFFFF, 0)
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#define DEVICE_ID UFS_MASK(0xFF, 24)
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/*
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* HCPMID - Host Controller Identification Descriptor
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* - Product/Manufacturer ID 14h
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*/
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#define MANUFACTURE_ID_MASK UFS_MASK(0xFFFF, 0)
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#define PRODUCT_ID_MASK UFS_MASK(0xFFFF, 16)
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/* AHIT - Auto-Hibernate Idle Timer */
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#define UFSHCI_AHIBERN8_TIMER_MASK GENMASK(9, 0)
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#define UFSHCI_AHIBERN8_SCALE_MASK GENMASK(12, 10)
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#define UFSHCI_AHIBERN8_SCALE_FACTOR 10
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#define UFSHCI_AHIBERN8_MAX (1023 * 100000)
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/*
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* IS - Interrupt Status - 20h
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*/
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#define UTP_TRANSFER_REQ_COMPL 0x1
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#define UIC_DME_END_PT_RESET 0x2
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#define UIC_ERROR 0x4
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#define UIC_TEST_MODE 0x8
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#define UIC_POWER_MODE 0x10
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#define UIC_HIBERNATE_EXIT 0x20
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#define UIC_HIBERNATE_ENTER 0x40
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#define UIC_LINK_LOST 0x80
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#define UIC_LINK_STARTUP 0x100
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#define UTP_TASK_REQ_COMPL 0x200
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#define UIC_COMMAND_COMPL 0x400
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#define DEVICE_FATAL_ERROR 0x800
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#define CONTROLLER_FATAL_ERROR 0x10000
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#define SYSTEM_BUS_FATAL_ERROR 0x20000
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#define CRYPTO_ENGINE_FATAL_ERROR 0x40000
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#define MCQ_CQ_EVENT_STATUS 0x100000
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#define UFSHCD_UIC_HIBERN8_MASK (UIC_HIBERNATE_ENTER |\
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UIC_HIBERNATE_EXIT)
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#define UFSHCD_UIC_PWR_MASK (UFSHCD_UIC_HIBERN8_MASK |\
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UIC_POWER_MODE)
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#define UFSHCD_UIC_MASK (UIC_COMMAND_COMPL | UFSHCD_UIC_PWR_MASK)
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#define UFSHCD_ERROR_MASK (UIC_ERROR | INT_FATAL_ERRORS)
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#define INT_FATAL_ERRORS (DEVICE_FATAL_ERROR |\
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CONTROLLER_FATAL_ERROR |\
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SYSTEM_BUS_FATAL_ERROR |\
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CRYPTO_ENGINE_FATAL_ERROR |\
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UIC_LINK_LOST)
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/* HCS - Host Controller Status 30h */
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#define DEVICE_PRESENT 0x1
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#define UTP_TRANSFER_REQ_LIST_READY 0x2
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#define UTP_TASK_REQ_LIST_READY 0x4
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#define UIC_COMMAND_READY 0x8
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#define HOST_ERROR_INDICATOR 0x10
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#define DEVICE_ERROR_INDICATOR 0x20
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#define UIC_POWER_MODE_CHANGE_REQ_STATUS_MASK UFS_MASK(0x7, 8)
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#define UFSHCD_STATUS_READY (UTP_TRANSFER_REQ_LIST_READY |\
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UTP_TASK_REQ_LIST_READY |\
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UIC_COMMAND_READY)
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enum {
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PWR_OK = 0x0,
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PWR_LOCAL = 0x01,
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PWR_REMOTE = 0x02,
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PWR_BUSY = 0x03,
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PWR_ERROR_CAP = 0x04,
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PWR_FATAL_ERROR = 0x05,
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};
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/* HCE - Host Controller Enable 34h */
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#define CONTROLLER_ENABLE 0x1
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#define CONTROLLER_DISABLE 0x0
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#define CRYPTO_GENERAL_ENABLE 0x2
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/* UECPA - Host UIC Error Code PHY Adapter Layer 38h */
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#define UIC_PHY_ADAPTER_LAYER_ERROR 0x80000000
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#define UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK 0x1F
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#define UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK 0xF
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#define UIC_PHY_ADAPTER_LAYER_GENERIC_ERROR 0x10
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/* UECDL - Host UIC Error Code Data Link Layer 3Ch */
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#define UIC_DATA_LINK_LAYER_ERROR 0x80000000
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#define UIC_DATA_LINK_LAYER_ERROR_CODE_MASK 0xFFFF
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#define UIC_DATA_LINK_LAYER_ERROR_TCX_REP_TIMER_EXP 0x2
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#define UIC_DATA_LINK_LAYER_ERROR_AFCX_REQ_TIMER_EXP 0x4
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#define UIC_DATA_LINK_LAYER_ERROR_FCX_PRO_TIMER_EXP 0x8
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#define UIC_DATA_LINK_LAYER_ERROR_RX_BUF_OF 0x20
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#define UIC_DATA_LINK_LAYER_ERROR_PA_INIT 0x2000
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#define UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED 0x0001
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#define UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT 0x0002
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/* UECN - Host UIC Error Code Network Layer 40h */
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#define UIC_NETWORK_LAYER_ERROR 0x80000000
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#define UIC_NETWORK_LAYER_ERROR_CODE_MASK 0x7
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#define UIC_NETWORK_UNSUPPORTED_HEADER_TYPE 0x1
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#define UIC_NETWORK_BAD_DEVICEID_ENC 0x2
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#define UIC_NETWORK_LHDR_TRAP_PACKET_DROPPING 0x4
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/* UECT - Host UIC Error Code Transport Layer 44h */
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#define UIC_TRANSPORT_LAYER_ERROR 0x80000000
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#define UIC_TRANSPORT_LAYER_ERROR_CODE_MASK 0x7F
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#define UIC_TRANSPORT_UNSUPPORTED_HEADER_TYPE 0x1
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#define UIC_TRANSPORT_UNKNOWN_CPORTID 0x2
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#define UIC_TRANSPORT_NO_CONNECTION_RX 0x4
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#define UIC_TRANSPORT_CONTROLLED_SEGMENT_DROPPING 0x8
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#define UIC_TRANSPORT_BAD_TC 0x10
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#define UIC_TRANSPORT_E2E_CREDIT_OVERFOW 0x20
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#define UIC_TRANSPORT_SAFETY_VALUE_DROPPING 0x40
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/* UECDME - Host UIC Error Code DME 48h */
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#define UIC_DME_ERROR 0x80000000
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#define UIC_DME_ERROR_CODE_MASK 0x1
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/* UTRIACR - Interrupt Aggregation control register - 0x4Ch */
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#define INT_AGGR_TIMEOUT_VAL_MASK 0xFF
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#define INT_AGGR_COUNTER_THRESHOLD_MASK UFS_MASK(0x1F, 8)
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#define INT_AGGR_COUNTER_AND_TIMER_RESET 0x10000
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#define INT_AGGR_STATUS_BIT 0x100000
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#define INT_AGGR_PARAM_WRITE 0x1000000
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#define INT_AGGR_ENABLE 0x80000000
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/* UTRLRSR - UTP Transfer Request Run-Stop Register 60h */
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#define UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT 0x1
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/* UTMRLRSR - UTP Task Management Request Run-Stop Register 80h */
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#define UTP_TASK_REQ_LIST_RUN_STOP_BIT 0x1
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/* CQISy - CQ y Interrupt Status Register */
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#define UFSHCD_MCQ_CQIS_TAIL_ENT_PUSH_STS 0x1
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/* UICCMD - UIC Command */
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#define COMMAND_OPCODE_MASK 0xFF
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#define GEN_SELECTOR_INDEX_MASK 0xFFFF
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#define MIB_ATTRIBUTE_MASK UFS_MASK(0xFFFF, 16)
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#define RESET_LEVEL 0xFF
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#define ATTR_SET_TYPE_MASK UFS_MASK(0xFF, 16)
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#define CONFIG_RESULT_CODE_MASK 0xFF
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#define GENERIC_ERROR_CODE_MASK 0xFF
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/* GenSelectorIndex calculation macros for M-PHY attributes */
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#define UIC_ARG_MPHY_TX_GEN_SEL_INDEX(lane) (lane)
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#define UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane) (PA_MAXDATALANES + (lane))
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#define UIC_ARG_MIB_SEL(attr, sel) ((((attr) & 0xFFFF) << 16) |\
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((sel) & 0xFFFF))
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#define UIC_ARG_MIB(attr) UIC_ARG_MIB_SEL(attr, 0)
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#define UIC_ARG_ATTR_TYPE(t) (((t) & 0xFF) << 16)
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#define UIC_GET_ATTR_ID(v) (((v) >> 16) & 0xFFFF)
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/* Link Status*/
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enum link_status {
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UFSHCD_LINK_IS_DOWN = 1,
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UFSHCD_LINK_IS_UP = 2,
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};
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/* UIC Commands */
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enum uic_cmd_dme {
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UIC_CMD_DME_GET = 0x01,
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UIC_CMD_DME_SET = 0x02,
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UIC_CMD_DME_PEER_GET = 0x03,
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UIC_CMD_DME_PEER_SET = 0x04,
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UIC_CMD_DME_POWERON = 0x10,
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UIC_CMD_DME_POWEROFF = 0x11,
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UIC_CMD_DME_ENABLE = 0x12,
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UIC_CMD_DME_RESET = 0x14,
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UIC_CMD_DME_END_PT_RST = 0x15,
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UIC_CMD_DME_LINK_STARTUP = 0x16,
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UIC_CMD_DME_HIBER_ENTER = 0x17,
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UIC_CMD_DME_HIBER_EXIT = 0x18,
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UIC_CMD_DME_TEST_MODE = 0x1A,
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};
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/* UIC Config result code / Generic error code */
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enum {
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UIC_CMD_RESULT_SUCCESS = 0x00,
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UIC_CMD_RESULT_INVALID_ATTR = 0x01,
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UIC_CMD_RESULT_FAILURE = 0x01,
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UIC_CMD_RESULT_INVALID_ATTR_VALUE = 0x02,
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UIC_CMD_RESULT_READ_ONLY_ATTR = 0x03,
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UIC_CMD_RESULT_WRITE_ONLY_ATTR = 0x04,
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UIC_CMD_RESULT_BAD_INDEX = 0x05,
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UIC_CMD_RESULT_LOCKED_ATTR = 0x06,
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UIC_CMD_RESULT_BAD_TEST_FEATURE_INDEX = 0x07,
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UIC_CMD_RESULT_PEER_COMM_FAILURE = 0x08,
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UIC_CMD_RESULT_BUSY = 0x09,
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UIC_CMD_RESULT_DME_FAILURE = 0x0A,
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};
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#define MASK_UIC_COMMAND_RESULT 0xFF
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#define INT_AGGR_COUNTER_THLD_VAL(c) (((c) & 0x1F) << 8)
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#define INT_AGGR_TIMEOUT_VAL(t) (((t) & 0xFF) << 0)
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/* Interrupt disable masks */
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enum {
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/* Interrupt disable mask for UFSHCI v1.0 */
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INTERRUPT_MASK_ALL_VER_10 = 0x30FFF,
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INTERRUPT_MASK_RW_VER_10 = 0x30000,
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/* Interrupt disable mask for UFSHCI v1.1 */
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INTERRUPT_MASK_ALL_VER_11 = 0x31FFF,
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/* Interrupt disable mask for UFSHCI v2.1 */
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INTERRUPT_MASK_ALL_VER_21 = 0x71FFF,
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};
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/* CCAP - Crypto Capability 100h */
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union ufs_crypto_capabilities {
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__le32 reg_val;
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struct {
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u8 num_crypto_cap;
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u8 config_count;
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u8 reserved;
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u8 config_array_ptr;
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};
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};
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enum ufs_crypto_key_size {
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UFS_CRYPTO_KEY_SIZE_INVALID = 0x0,
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UFS_CRYPTO_KEY_SIZE_128 = 0x1,
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UFS_CRYPTO_KEY_SIZE_192 = 0x2,
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UFS_CRYPTO_KEY_SIZE_256 = 0x3,
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UFS_CRYPTO_KEY_SIZE_512 = 0x4,
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};
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enum ufs_crypto_alg {
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UFS_CRYPTO_ALG_AES_XTS = 0x0,
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UFS_CRYPTO_ALG_BITLOCKER_AES_CBC = 0x1,
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UFS_CRYPTO_ALG_AES_ECB = 0x2,
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UFS_CRYPTO_ALG_ESSIV_AES_CBC = 0x3,
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};
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/* x-CRYPTOCAP - Crypto Capability X */
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union ufs_crypto_cap_entry {
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__le32 reg_val;
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struct {
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u8 algorithm_id;
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u8 sdus_mask; /* Supported data unit size mask */
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u8 key_size;
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u8 reserved;
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};
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};
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#define UFS_CRYPTO_CONFIGURATION_ENABLE (1 << 7)
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#define UFS_CRYPTO_KEY_MAX_SIZE 64
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/* x-CRYPTOCFG - Crypto Configuration X */
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union ufs_crypto_cfg_entry {
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__le32 reg_val[32];
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struct {
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u8 crypto_key[UFS_CRYPTO_KEY_MAX_SIZE];
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u8 data_unit_size;
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u8 crypto_cap_idx;
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u8 reserved_1;
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u8 config_enable;
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u8 reserved_multi_host;
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u8 reserved_2;
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u8 vsb[2];
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u8 reserved_3[56];
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};
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};
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/*
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* Request Descriptor Definitions
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*/
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/* Transfer request command type */
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enum {
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UTP_CMD_TYPE_SCSI = 0x0,
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UTP_CMD_TYPE_UFS = 0x1,
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UTP_CMD_TYPE_DEV_MANAGE = 0x2,
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};
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/* To accommodate UFS2.0 required Command type */
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enum {
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UTP_CMD_TYPE_UFS_STORAGE = 0x1,
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};
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enum {
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UTP_SCSI_COMMAND = 0x00000000,
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UTP_NATIVE_UFS_COMMAND = 0x10000000,
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UTP_DEVICE_MANAGEMENT_FUNCTION = 0x20000000,
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};
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/* UTP Transfer Request Data Direction (DD) */
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enum utp_data_direction {
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|
UTP_NO_DATA_TRANSFER = 0,
|
|
UTP_HOST_TO_DEVICE = 1,
|
|
UTP_DEVICE_TO_HOST = 2,
|
|
};
|
|
|
|
/* Overall command status values */
|
|
enum utp_ocs {
|
|
OCS_SUCCESS = 0x0,
|
|
OCS_INVALID_CMD_TABLE_ATTR = 0x1,
|
|
OCS_INVALID_PRDT_ATTR = 0x2,
|
|
OCS_MISMATCH_DATA_BUF_SIZE = 0x3,
|
|
OCS_MISMATCH_RESP_UPIU_SIZE = 0x4,
|
|
OCS_PEER_COMM_FAILURE = 0x5,
|
|
OCS_ABORTED = 0x6,
|
|
OCS_FATAL_ERROR = 0x7,
|
|
OCS_DEVICE_FATAL_ERROR = 0x8,
|
|
OCS_INVALID_CRYPTO_CONFIG = 0x9,
|
|
OCS_GENERAL_CRYPTO_ERROR = 0xA,
|
|
OCS_INVALID_COMMAND_STATUS = 0x0F,
|
|
};
|
|
|
|
enum {
|
|
MASK_OCS = 0x0F,
|
|
};
|
|
|
|
/* The maximum length of the data byte count field in the PRDT is 256KB */
|
|
#define PRDT_DATA_BYTE_COUNT_MAX SZ_256K
|
|
/* The granularity of the data byte count field in the PRDT is 32-bit */
|
|
#define PRDT_DATA_BYTE_COUNT_PAD 4
|
|
|
|
/**
|
|
* struct ufshcd_sg_entry - UFSHCI PRD Entry
|
|
* @addr: Physical address; DW-0 and DW-1.
|
|
* @reserved: Reserved for future use DW-2
|
|
* @size: size of physical segment DW-3
|
|
*/
|
|
struct ufshcd_sg_entry {
|
|
__le64 addr;
|
|
__le32 reserved;
|
|
__le32 size;
|
|
/*
|
|
* followed by variant-specific fields if
|
|
* CONFIG_SCSI_UFS_VARIABLE_SG_ENTRY_SIZE has been defined.
|
|
*/
|
|
};
|
|
|
|
/**
|
|
* struct utp_transfer_cmd_desc - UTP Command Descriptor (UCD)
|
|
* @command_upiu: Command UPIU Frame address
|
|
* @response_upiu: Response UPIU Frame address
|
|
* @prd_table: Physical Region Descriptor: an array of SG_ALL struct
|
|
* ufshcd_sg_entry's. Variant-specific fields may be present after each.
|
|
*/
|
|
struct utp_transfer_cmd_desc {
|
|
u8 command_upiu[ALIGNED_UPIU_SIZE];
|
|
u8 response_upiu[ALIGNED_UPIU_SIZE];
|
|
u8 prd_table[];
|
|
};
|
|
|
|
/**
|
|
* struct request_desc_header - Descriptor Header common to both UTRD and UTMRD
|
|
*/
|
|
struct request_desc_header {
|
|
u8 cci;
|
|
u8 ehs_length;
|
|
#if defined(__BIG_ENDIAN)
|
|
u8 enable_crypto:1;
|
|
u8 reserved2:7;
|
|
|
|
u8 command_type:4;
|
|
u8 reserved1:1;
|
|
u8 data_direction:2;
|
|
u8 interrupt:1;
|
|
#elif defined(__LITTLE_ENDIAN)
|
|
u8 reserved2:7;
|
|
u8 enable_crypto:1;
|
|
|
|
u8 interrupt:1;
|
|
u8 data_direction:2;
|
|
u8 reserved1:1;
|
|
u8 command_type:4;
|
|
#else
|
|
#error
|
|
#endif
|
|
|
|
__le32 dunl;
|
|
u8 ocs;
|
|
u8 cds;
|
|
__le16 ldbc;
|
|
__le32 dunu;
|
|
};
|
|
|
|
static_assert(sizeof(struct request_desc_header) == 16);
|
|
|
|
/**
|
|
* struct utp_transfer_req_desc - UTP Transfer Request Descriptor (UTRD)
|
|
* @header: UTRD header DW-0 to DW-3
|
|
* @command_desc_base_addr: UCD base address DW 4-5
|
|
* @response_upiu_length: response UPIU length DW-6
|
|
* @response_upiu_offset: response UPIU offset DW-6
|
|
* @prd_table_length: Physical region descriptor length DW-7
|
|
* @prd_table_offset: Physical region descriptor offset DW-7
|
|
*/
|
|
struct utp_transfer_req_desc {
|
|
|
|
/* DW 0-3 */
|
|
struct request_desc_header header;
|
|
|
|
/* DW 4-5*/
|
|
__le64 command_desc_base_addr;
|
|
|
|
/* DW 6 */
|
|
__le16 response_upiu_length;
|
|
__le16 response_upiu_offset;
|
|
|
|
/* DW 7 */
|
|
__le16 prd_table_length;
|
|
__le16 prd_table_offset;
|
|
};
|
|
|
|
/* MCQ Completion Queue Entry */
|
|
struct cq_entry {
|
|
/* DW 0-1 */
|
|
__le64 command_desc_base_addr;
|
|
|
|
/* DW 2 */
|
|
__le16 response_upiu_length;
|
|
__le16 response_upiu_offset;
|
|
|
|
/* DW 3 */
|
|
__le16 prd_table_length;
|
|
__le16 prd_table_offset;
|
|
|
|
/* DW 4 */
|
|
__le32 status;
|
|
|
|
/* DW 5-7 */
|
|
__le32 reserved[3];
|
|
};
|
|
|
|
static_assert(sizeof(struct cq_entry) == 32);
|
|
|
|
/*
|
|
* UTMRD structure.
|
|
*/
|
|
struct utp_task_req_desc {
|
|
/* DW 0-3 */
|
|
struct request_desc_header header;
|
|
|
|
/* DW 4-11 - Task request UPIU structure */
|
|
struct {
|
|
struct utp_upiu_header req_header;
|
|
__be32 input_param1;
|
|
__be32 input_param2;
|
|
__be32 input_param3;
|
|
__be32 __reserved1[2];
|
|
} upiu_req;
|
|
|
|
/* DW 12-19 - Task Management Response UPIU structure */
|
|
struct {
|
|
struct utp_upiu_header rsp_header;
|
|
__be32 output_param1;
|
|
__be32 output_param2;
|
|
__be32 __reserved2[3];
|
|
} upiu_rsp;
|
|
};
|
|
|
|
#endif /* End of Header */
|