201 lines
3.8 KiB
C
201 lines
3.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
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/* Copyright (c) 2021, Microsoft Corporation. */
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#ifndef _HW_CHANNEL_H
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#define _HW_CHANNEL_H
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#define DEFAULT_LOG2_THROTTLING_FOR_ERROR_EQ 4
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#define HW_CHANNEL_MAX_REQUEST_SIZE 0x1000
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#define HW_CHANNEL_MAX_RESPONSE_SIZE 0x1000
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#define HW_CHANNEL_VF_BOOTSTRAP_QUEUE_DEPTH 1
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#define HWC_INIT_DATA_CQID 1
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#define HWC_INIT_DATA_RQID 2
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#define HWC_INIT_DATA_SQID 3
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#define HWC_INIT_DATA_QUEUE_DEPTH 4
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#define HWC_INIT_DATA_MAX_REQUEST 5
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#define HWC_INIT_DATA_MAX_RESPONSE 6
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#define HWC_INIT_DATA_MAX_NUM_CQS 7
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#define HWC_INIT_DATA_PDID 8
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#define HWC_INIT_DATA_GPA_MKEY 9
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#define HWC_INIT_DATA_PF_DEST_RQ_ID 10
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#define HWC_INIT_DATA_PF_DEST_CQ_ID 11
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#define HWC_DATA_CFG_HWC_TIMEOUT 1
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#define HW_CHANNEL_WAIT_RESOURCE_TIMEOUT_MS 30000
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/* Structures labeled with "HW DATA" are exchanged with the hardware. All of
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* them are naturally aligned and hence don't need __packed.
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*/
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union hwc_init_eq_id_db {
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u32 as_uint32;
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struct {
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u32 eq_id : 16;
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u32 doorbell : 16;
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};
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}; /* HW DATA */
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union hwc_init_type_data {
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u32 as_uint32;
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struct {
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u32 value : 24;
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u32 type : 8;
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};
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}; /* HW DATA */
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struct hwc_rx_oob {
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u32 type : 6;
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u32 eom : 1;
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u32 som : 1;
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u32 vendor_err : 8;
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u32 reserved1 : 16;
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u32 src_virt_wq : 24;
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u32 src_vfid : 8;
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u32 reserved2;
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union {
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u32 wqe_addr_low;
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u32 wqe_offset;
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};
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u32 wqe_addr_high;
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u32 client_data_unit : 14;
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u32 reserved3 : 18;
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u32 tx_oob_data_size;
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u32 chunk_offset : 21;
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u32 reserved4 : 11;
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}; /* HW DATA */
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struct hwc_tx_oob {
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u32 reserved1;
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u32 reserved2;
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u32 vrq_id : 24;
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u32 dest_vfid : 8;
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u32 vrcq_id : 24;
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u32 reserved3 : 8;
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u32 vscq_id : 24;
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u32 loopback : 1;
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u32 lso_override: 1;
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u32 dest_pf : 1;
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u32 reserved4 : 5;
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u32 vsq_id : 24;
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u32 reserved5 : 8;
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}; /* HW DATA */
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struct hwc_work_request {
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void *buf_va;
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void *buf_sge_addr;
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u32 buf_len;
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u32 msg_size;
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struct gdma_wqe_request wqe_req;
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struct hwc_tx_oob tx_oob;
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struct gdma_sge sge;
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};
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/* hwc_dma_buf represents the array of in-flight WQEs.
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* mem_info as know as the GDMA mapped memory is partitioned and used by
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* in-flight WQEs.
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* The number of WQEs is determined by the number of in-flight messages.
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*/
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struct hwc_dma_buf {
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struct gdma_mem_info mem_info;
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u32 gpa_mkey;
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u32 num_reqs;
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struct hwc_work_request reqs[] __counted_by(num_reqs);
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};
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typedef void hwc_rx_event_handler_t(void *ctx, u32 gdma_rxq_id,
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const struct hwc_rx_oob *rx_oob);
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typedef void hwc_tx_event_handler_t(void *ctx, u32 gdma_txq_id,
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const struct hwc_rx_oob *rx_oob);
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struct hwc_cq {
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struct hw_channel_context *hwc;
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struct gdma_queue *gdma_cq;
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struct gdma_queue *gdma_eq;
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struct gdma_comp *comp_buf;
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u16 queue_depth;
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hwc_rx_event_handler_t *rx_event_handler;
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void *rx_event_ctx;
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hwc_tx_event_handler_t *tx_event_handler;
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void *tx_event_ctx;
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};
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struct hwc_wq {
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struct hw_channel_context *hwc;
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struct gdma_queue *gdma_wq;
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struct hwc_dma_buf *msg_buf;
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u16 queue_depth;
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struct hwc_cq *hwc_cq;
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};
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struct hwc_caller_ctx {
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struct completion comp_event;
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void *output_buf;
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u32 output_buflen;
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u32 error; /* Linux error code */
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u32 status_code;
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};
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struct hw_channel_context {
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struct gdma_dev *gdma_dev;
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struct device *dev;
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u16 num_inflight_msg;
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u32 max_req_msg_size;
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u16 hwc_init_q_depth_max;
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u32 hwc_init_max_req_msg_size;
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u32 hwc_init_max_resp_msg_size;
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struct completion hwc_init_eqe_comp;
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struct hwc_wq *rxq;
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struct hwc_wq *txq;
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struct hwc_cq *cq;
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struct semaphore sema;
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struct gdma_resource inflight_msg_res;
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u32 pf_dest_vrq_id;
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u32 pf_dest_vrcq_id;
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u32 hwc_timeout;
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struct hwc_caller_ctx *caller_ctx;
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};
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int mana_hwc_create_channel(struct gdma_context *gc);
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void mana_hwc_destroy_channel(struct gdma_context *gc);
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int mana_hwc_send_request(struct hw_channel_context *hwc, u32 req_len,
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const void *req, u32 resp_len, void *resp);
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#endif /* _HW_CHANNEL_H */
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