250 lines
6.2 KiB
C
250 lines
6.2 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Real time clocks driver for MStar/SigmaStar SSD202D SoCs.
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*
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* (C) 2021 Daniel Palmer
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* (C) 2023 Romain Perier
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/module.h>
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#include <linux/mod_devicetable.h>
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#include <linux/platform_device.h>
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#include <linux/rtc.h>
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#include <linux/regmap.h>
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#include <linux/pm.h>
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#define REG_CTRL 0x0
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#define REG_CTRL1 0x4
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#define REG_ISO_CTRL 0xc
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#define REG_WRDATA_L 0x10
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#define REG_WRDATA_H 0x14
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#define REG_ISOACK 0x20
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#define REG_RDDATA_L 0x24
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#define REG_RDDATA_H 0x28
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#define REG_RDCNT_L 0x30
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#define REG_RDCNT_H 0x34
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#define REG_CNT_TRIG 0x38
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#define REG_PWRCTRL 0x3c
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#define REG_RTC_TEST 0x54
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#define CNT_RD_TRIG_BIT BIT(0)
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#define CNT_RD_BIT BIT(0)
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#define BASE_WR_BIT BIT(1)
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#define BASE_RD_BIT BIT(2)
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#define CNT_RST_BIT BIT(3)
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#define ISO_CTRL_ACK_MASK BIT(3)
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#define ISO_CTRL_ACK_SHIFT 3
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#define SW0_WR_BIT BIT(5)
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#define SW1_WR_BIT BIT(6)
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#define SW0_RD_BIT BIT(7)
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#define SW1_RD_BIT BIT(8)
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#define ISO_CTRL_MASK GENMASK(2, 0)
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struct ssd202d_rtc {
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struct rtc_device *rtc_dev;
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void __iomem *base;
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};
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static u8 read_iso_en(void __iomem *base)
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{
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return readb(base + REG_RTC_TEST) & 0x1;
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}
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static u8 read_iso_ctrl_ack(void __iomem *base)
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{
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return (readb(base + REG_ISOACK) & ISO_CTRL_ACK_MASK) >> ISO_CTRL_ACK_SHIFT;
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}
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static int ssd202d_rtc_isoctrl(struct ssd202d_rtc *priv)
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{
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static const unsigned int sequence[] = { 0x0, 0x1, 0x3, 0x7, 0x5, 0x1, 0x0 };
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unsigned int val;
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struct device *dev = &priv->rtc_dev->dev;
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int i, ret;
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/*
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* This gates iso_en by writing a special sequence of bytes to iso_ctrl
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* and ensuring that it has been correctly applied by reading iso_ctrl_ack
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*/
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for (i = 0; i < ARRAY_SIZE(sequence); i++) {
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writeb(sequence[i] & ISO_CTRL_MASK, priv->base + REG_ISO_CTRL);
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ret = read_poll_timeout(read_iso_ctrl_ack, val, val == (i % 2), 100,
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20 * 100, true, priv->base);
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if (ret) {
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dev_dbg(dev, "Timeout waiting for ack byte %i (%x) of sequence\n", i,
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sequence[i]);
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return ret;
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}
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}
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/*
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* At this point iso_en should be raised for 1ms
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*/
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ret = read_poll_timeout(read_iso_en, val, val, 100, 22 * 100, true, priv->base);
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if (ret)
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dev_dbg(dev, "Timeout waiting for iso_en\n");
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mdelay(2);
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return 0;
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}
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static void ssd202d_rtc_read_reg(struct ssd202d_rtc *priv, unsigned int reg,
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unsigned int field, unsigned int *base)
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{
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unsigned int l, h;
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u16 val;
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/* Ask for the content of an RTC value into RDDATA by gating iso_en,
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* then iso_en is gated and the content of RDDATA can be read
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*/
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val = readw(priv->base + reg);
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writew(val | field, priv->base + reg);
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ssd202d_rtc_isoctrl(priv);
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writew(val & ~field, priv->base + reg);
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l = readw(priv->base + REG_RDDATA_L);
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h = readw(priv->base + REG_RDDATA_H);
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*base = (h << 16) | l;
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}
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static void ssd202d_rtc_write_reg(struct ssd202d_rtc *priv, unsigned int reg,
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unsigned int field, u32 base)
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{
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u16 val;
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/* Set the content of an RTC value from WRDATA by gating iso_en */
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val = readw(priv->base + reg);
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writew(val | field, priv->base + reg);
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writew(base, priv->base + REG_WRDATA_L);
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writew(base >> 16, priv->base + REG_WRDATA_H);
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ssd202d_rtc_isoctrl(priv);
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writew(val & ~field, priv->base + reg);
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}
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static int ssd202d_rtc_read_counter(struct ssd202d_rtc *priv, unsigned int *counter)
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{
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unsigned int l, h;
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u16 val;
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val = readw(priv->base + REG_CTRL1);
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writew(val | CNT_RD_BIT, priv->base + REG_CTRL1);
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ssd202d_rtc_isoctrl(priv);
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writew(val & ~CNT_RD_BIT, priv->base + REG_CTRL1);
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val = readw(priv->base + REG_CTRL1);
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writew(val | CNT_RD_TRIG_BIT, priv->base + REG_CNT_TRIG);
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writew(val & ~CNT_RD_TRIG_BIT, priv->base + REG_CNT_TRIG);
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l = readw(priv->base + REG_RDCNT_L);
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h = readw(priv->base + REG_RDCNT_H);
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*counter = (h << 16) | l;
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return 0;
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}
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static int ssd202d_rtc_read_time(struct device *dev, struct rtc_time *tm)
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{
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struct ssd202d_rtc *priv = dev_get_drvdata(dev);
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unsigned int sw0, base, counter;
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u32 seconds;
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int ret;
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/* Check that RTC is enabled by SW */
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ssd202d_rtc_read_reg(priv, REG_CTRL, SW0_RD_BIT, &sw0);
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if (sw0 != 1)
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return -EINVAL;
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/* Get RTC base value from RDDATA */
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ssd202d_rtc_read_reg(priv, REG_CTRL, BASE_RD_BIT, &base);
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/* Get RTC counter value from RDDATA */
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ret = ssd202d_rtc_read_counter(priv, &counter);
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if (ret)
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return ret;
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seconds = base + counter;
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rtc_time64_to_tm(seconds, tm);
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return 0;
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}
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static int ssd202d_rtc_reset_counter(struct ssd202d_rtc *priv)
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{
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u16 val;
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val = readw(priv->base + REG_CTRL);
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writew(val | CNT_RST_BIT, priv->base + REG_CTRL);
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ssd202d_rtc_isoctrl(priv);
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writew(val & ~CNT_RST_BIT, priv->base + REG_CTRL);
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ssd202d_rtc_isoctrl(priv);
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return 0;
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}
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static int ssd202d_rtc_set_time(struct device *dev, struct rtc_time *tm)
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{
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struct ssd202d_rtc *priv = dev_get_drvdata(dev);
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unsigned long seconds = rtc_tm_to_time64(tm);
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ssd202d_rtc_write_reg(priv, REG_CTRL, BASE_WR_BIT, seconds);
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ssd202d_rtc_reset_counter(priv);
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ssd202d_rtc_write_reg(priv, REG_CTRL, SW0_WR_BIT, 1);
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return 0;
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}
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static const struct rtc_class_ops ssd202d_rtc_ops = {
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.read_time = ssd202d_rtc_read_time,
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.set_time = ssd202d_rtc_set_time,
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};
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static int ssd202d_rtc_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct ssd202d_rtc *priv;
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priv = devm_kzalloc(&pdev->dev, sizeof(struct ssd202d_rtc), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(priv->base))
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return PTR_ERR(priv->base);
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priv->rtc_dev = devm_rtc_allocate_device(dev);
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if (IS_ERR(priv->rtc_dev))
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return PTR_ERR(priv->rtc_dev);
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priv->rtc_dev->ops = &ssd202d_rtc_ops;
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priv->rtc_dev->range_max = U32_MAX;
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platform_set_drvdata(pdev, priv);
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return devm_rtc_register_device(priv->rtc_dev);
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}
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static const struct of_device_id ssd202d_rtc_of_match_table[] = {
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{ .compatible = "mstar,ssd202d-rtc" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, ssd202d_rtc_of_match_table);
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static struct platform_driver ssd202d_rtc_driver = {
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.probe = ssd202d_rtc_probe,
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.driver = {
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.name = "ssd202d-rtc",
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.of_match_table = ssd202d_rtc_of_match_table,
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},
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};
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module_platform_driver(ssd202d_rtc_driver);
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MODULE_AUTHOR("Daniel Palmer <daniel@thingy.jp>");
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MODULE_AUTHOR("Romain Perier <romain.perier@gmail.com>");
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MODULE_DESCRIPTION("MStar SSD202D RTC Driver");
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MODULE_LICENSE("GPL");
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