169 lines
4.9 KiB
C
169 lines
4.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2009-2010 Advanced Micro Devices, Inc.
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* Author: Joerg Roedel <jroedel@suse.de>
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*/
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#ifndef AMD_IOMMU_H
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#define AMD_IOMMU_H
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#include <linux/iommu.h>
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#include "amd_iommu_types.h"
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irqreturn_t amd_iommu_int_thread(int irq, void *data);
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irqreturn_t amd_iommu_int_thread_evtlog(int irq, void *data);
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irqreturn_t amd_iommu_int_thread_pprlog(int irq, void *data);
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irqreturn_t amd_iommu_int_thread_galog(int irq, void *data);
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irqreturn_t amd_iommu_int_handler(int irq, void *data);
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void amd_iommu_apply_erratum_63(struct amd_iommu *iommu, u16 devid);
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void amd_iommu_restart_event_logging(struct amd_iommu *iommu);
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void amd_iommu_restart_ga_log(struct amd_iommu *iommu);
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void amd_iommu_restart_ppr_log(struct amd_iommu *iommu);
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void amd_iommu_set_rlookup_table(struct amd_iommu *iommu, u16 devid);
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#ifdef CONFIG_AMD_IOMMU_DEBUGFS
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void amd_iommu_debugfs_setup(struct amd_iommu *iommu);
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#else
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static inline void amd_iommu_debugfs_setup(struct amd_iommu *iommu) {}
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#endif
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/* Needed for interrupt remapping */
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int amd_iommu_prepare(void);
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int amd_iommu_enable(void);
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void amd_iommu_disable(void);
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int amd_iommu_reenable(int mode);
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int amd_iommu_enable_faulting(void);
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extern int amd_iommu_guest_ir;
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extern enum io_pgtable_fmt amd_iommu_pgtable;
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extern int amd_iommu_gpt_level;
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bool amd_iommu_v2_supported(void);
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struct amd_iommu *get_amd_iommu(unsigned int idx);
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u8 amd_iommu_pc_get_max_banks(unsigned int idx);
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bool amd_iommu_pc_supported(void);
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u8 amd_iommu_pc_get_max_counters(unsigned int idx);
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int amd_iommu_pc_get_reg(struct amd_iommu *iommu, u8 bank, u8 cntr,
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u8 fxn, u64 *value);
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int amd_iommu_pc_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr,
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u8 fxn, u64 *value);
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/* Device capabilities */
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int amd_iommu_pdev_enable_cap_pri(struct pci_dev *pdev);
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void amd_iommu_pdev_disable_cap_pri(struct pci_dev *pdev);
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int amd_iommu_flush_page(struct iommu_domain *dom, u32 pasid, u64 address);
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/*
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* This function flushes all internal caches of
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* the IOMMU used by this driver.
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*/
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void amd_iommu_flush_all_caches(struct amd_iommu *iommu);
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void amd_iommu_update_and_flush_device_table(struct protection_domain *domain);
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void amd_iommu_domain_update(struct protection_domain *domain);
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void amd_iommu_domain_flush_complete(struct protection_domain *domain);
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void amd_iommu_domain_flush_pages(struct protection_domain *domain,
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u64 address, size_t size);
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int amd_iommu_flush_tlb(struct iommu_domain *dom, u32 pasid);
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int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, u32 pasid,
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unsigned long cr3);
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int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, u32 pasid);
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#ifdef CONFIG_IRQ_REMAP
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int amd_iommu_create_irq_domain(struct amd_iommu *iommu);
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#else
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static inline int amd_iommu_create_irq_domain(struct amd_iommu *iommu)
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{
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return 0;
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}
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#endif
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#define PPR_SUCCESS 0x0
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#define PPR_INVALID 0x1
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#define PPR_FAILURE 0xf
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int amd_iommu_complete_ppr(struct pci_dev *pdev, u32 pasid,
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int status, int tag);
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static inline bool is_rd890_iommu(struct pci_dev *pdev)
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{
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return (pdev->vendor == PCI_VENDOR_ID_ATI) &&
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(pdev->device == PCI_DEVICE_ID_RD890_IOMMU);
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}
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static inline bool check_feature(u64 mask)
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{
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return (amd_iommu_efr & mask);
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}
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static inline bool check_feature2(u64 mask)
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{
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return (amd_iommu_efr2 & mask);
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}
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static inline int check_feature_gpt_level(void)
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{
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return ((amd_iommu_efr >> FEATURE_GATS_SHIFT) & FEATURE_GATS_MASK);
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}
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static inline bool amd_iommu_gt_ppr_supported(void)
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{
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return (check_feature(FEATURE_GT) &&
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check_feature(FEATURE_PPR));
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}
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static inline u64 iommu_virt_to_phys(void *vaddr)
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{
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return (u64)__sme_set(virt_to_phys(vaddr));
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}
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static inline void *iommu_phys_to_virt(unsigned long paddr)
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{
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return phys_to_virt(__sme_clr(paddr));
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}
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static inline
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void amd_iommu_domain_set_pt_root(struct protection_domain *domain, u64 root)
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{
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domain->iop.root = (u64 *)(root & PAGE_MASK);
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domain->iop.mode = root & 7; /* lowest 3 bits encode pgtable mode */
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}
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static inline
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void amd_iommu_domain_clr_pt_root(struct protection_domain *domain)
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{
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amd_iommu_domain_set_pt_root(domain, 0);
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}
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static inline int get_pci_sbdf_id(struct pci_dev *pdev)
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{
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int seg = pci_domain_nr(pdev->bus);
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u16 devid = pci_dev_id(pdev);
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return PCI_SEG_DEVID_TO_SBDF(seg, devid);
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}
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static inline void *alloc_pgtable_page(int nid, gfp_t gfp)
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{
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struct page *page;
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page = alloc_pages_node(nid, gfp | __GFP_ZERO, 0);
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return page ? page_address(page) : NULL;
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}
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bool translation_pre_enabled(struct amd_iommu *iommu);
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bool amd_iommu_is_attach_deferred(struct device *dev);
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int __init add_special_device(u8 type, u8 id, u32 *devid, bool cmd_line);
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#ifdef CONFIG_DMI
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void amd_iommu_apply_ivrs_quirks(void);
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#else
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static inline void amd_iommu_apply_ivrs_quirks(void) { }
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#endif
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void amd_iommu_domain_set_pgtable(struct protection_domain *domain,
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u64 *root, int mode);
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struct dev_table_entry *get_dev_table(struct amd_iommu *iommu);
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extern bool amd_iommu_snp_en;
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#endif
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