342 lines
10 KiB
C
342 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Marvell PXA25x family clocks
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*
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* Copyright (C) 2014 Robert Jarzmik
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*
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* Heavily inspired from former arch/arm/mach-pxa/pxa25x.c.
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*
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* For non-devicetree platforms. Once pxa is fully converted to devicetree, this
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* should go away.
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*/
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#include <linux/clk-provider.h>
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#include <linux/clk.h>
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#include <linux/clk/pxa.h>
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#include <linux/clkdev.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/soc/pxa/smemc.h>
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#include <linux/soc/pxa/cpu.h>
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#include <dt-bindings/clock/pxa-clock.h>
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#include "clk-pxa.h"
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#include "clk-pxa2xx.h"
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#define KHz 1000
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#define MHz (1000 * 1000)
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enum {
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PXA_CORE_RUN = 0,
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PXA_CORE_TURBO,
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};
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#define PXA25x_CLKCFG(T) \
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(CLKCFG_FCS | \
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((T) ? CLKCFG_TURBO : 0))
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#define PXA25x_CCCR(N2, M, L) (N2 << 7 | M << 5 | L)
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/* Define the refresh period in mSec for the SDRAM and the number of rows */
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#define SDRAM_TREF 64 /* standard 64ms SDRAM */
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/*
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* Various clock factors driven by the CCCR register.
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*/
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static void __iomem *clk_regs;
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/* Crystal Frequency to Memory Frequency Multiplier (L) */
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static unsigned char L_clk_mult[32] = { 0, 27, 32, 36, 40, 45, 0, };
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/* Memory Frequency to Run Mode Frequency Multiplier (M) */
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static unsigned char M_clk_mult[4] = { 0, 1, 2, 4 };
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/* Run Mode Frequency to Turbo Mode Frequency Multiplier (N) */
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/* Note: we store the value N * 2 here. */
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static unsigned char N2_clk_mult[8] = { 0, 0, 2, 3, 4, 0, 6, 0 };
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static const char * const get_freq_khz[] = {
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"core", "run", "cpll", "memory"
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};
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static u32 mdrefr_dri(unsigned int freq_khz)
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{
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u32 interval = freq_khz * SDRAM_TREF / pxa2xx_smemc_get_sdram_rows();
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return interval / 32;
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}
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/*
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* Get the clock frequency as reflected by CCCR and the turbo flag.
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* We assume these values have been applied via a fcs.
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* If info is not 0 we also display the current settings.
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*/
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unsigned int pxa25x_get_clk_frequency_khz(int info)
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{
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struct clk *clk;
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unsigned long clks[5];
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int i;
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for (i = 0; i < ARRAY_SIZE(get_freq_khz); i++) {
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clk = clk_get(NULL, get_freq_khz[i]);
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if (IS_ERR(clk)) {
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clks[i] = 0;
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} else {
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clks[i] = clk_get_rate(clk);
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clk_put(clk);
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}
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}
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if (info) {
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pr_info("Run Mode clock: %ld.%02ldMHz\n",
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clks[1] / 1000000, (clks[1] % 1000000) / 10000);
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pr_info("Turbo Mode clock: %ld.%02ldMHz\n",
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clks[2] / 1000000, (clks[2] % 1000000) / 10000);
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pr_info("Memory clock: %ld.%02ldMHz\n",
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clks[3] / 1000000, (clks[3] % 1000000) / 10000);
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}
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return (unsigned int)clks[0] / KHz;
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}
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static unsigned long clk_pxa25x_memory_get_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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unsigned long cccr = readl(clk_regs + CCCR);
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unsigned int m = M_clk_mult[(cccr >> 5) & 0x03];
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return parent_rate / m;
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}
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PARENTS(clk_pxa25x_memory) = { "run" };
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RATE_RO_OPS(clk_pxa25x_memory, "memory");
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PARENTS(pxa25x_pbus95) = { "ppll_95_85mhz", "ppll_95_85mhz" };
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PARENTS(pxa25x_pbus147) = { "ppll_147_46mhz", "ppll_147_46mhz" };
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PARENTS(pxa25x_osc3) = { "osc_3_6864mhz", "osc_3_6864mhz" };
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#define PXA25X_CKEN(dev_id, con_id, parents, mult, div, \
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bit, is_lp, flags) \
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PXA_CKEN(dev_id, con_id, bit, parents, mult, div, mult, div, \
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is_lp, CKEN, CKEN_ ## bit, flags)
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#define PXA25X_PBUS95_CKEN(dev_id, con_id, bit, mult_hp, div_hp, delay) \
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PXA25X_CKEN(dev_id, con_id, pxa25x_pbus95_parents, mult_hp, \
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div_hp, bit, NULL, 0)
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#define PXA25X_PBUS147_CKEN(dev_id, con_id, bit, mult_hp, div_hp, delay)\
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PXA25X_CKEN(dev_id, con_id, pxa25x_pbus147_parents, mult_hp, \
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div_hp, bit, NULL, 0)
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#define PXA25X_OSC3_CKEN(dev_id, con_id, bit, mult_hp, div_hp, delay) \
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PXA25X_CKEN(dev_id, con_id, pxa25x_osc3_parents, mult_hp, \
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div_hp, bit, NULL, 0)
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#define PXA25X_CKEN_1RATE(dev_id, con_id, bit, parents, delay) \
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PXA_CKEN_1RATE(dev_id, con_id, bit, parents, \
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CKEN, CKEN_ ## bit, 0)
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#define PXA25X_CKEN_1RATE_AO(dev_id, con_id, bit, parents, delay) \
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PXA_CKEN_1RATE(dev_id, con_id, bit, parents, \
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CKEN, CKEN_ ## bit, CLK_IGNORE_UNUSED)
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static struct desc_clk_cken pxa25x_clocks[] __initdata = {
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PXA25X_PBUS95_CKEN("pxa2xx-mci.0", NULL, MMC, 1, 5, 0),
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PXA25X_PBUS95_CKEN("pxa2xx-i2c.0", NULL, I2C, 1, 3, 0),
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PXA25X_PBUS95_CKEN("pxa2xx-ir", "FICPCLK", FICP, 1, 2, 0),
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PXA25X_PBUS95_CKEN("pxa25x-udc", NULL, USB, 1, 2, 5),
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PXA25X_PBUS147_CKEN("pxa2xx-uart.0", NULL, FFUART, 1, 10, 1),
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PXA25X_PBUS147_CKEN("pxa2xx-uart.1", NULL, BTUART, 1, 10, 1),
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PXA25X_PBUS147_CKEN("pxa2xx-uart.2", NULL, STUART, 1, 10, 1),
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PXA25X_PBUS147_CKEN("pxa2xx-uart.3", NULL, HWUART, 1, 10, 1),
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PXA25X_PBUS147_CKEN("pxa2xx-i2s", NULL, I2S, 1, 10, 0),
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PXA25X_PBUS147_CKEN(NULL, "AC97CLK", AC97, 1, 12, 0),
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PXA25X_OSC3_CKEN("pxa25x-ssp.0", NULL, SSP, 1, 1, 0),
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PXA25X_OSC3_CKEN("pxa25x-nssp.1", NULL, NSSP, 1, 1, 0),
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PXA25X_OSC3_CKEN("pxa25x-nssp.2", NULL, ASSP, 1, 1, 0),
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PXA25X_OSC3_CKEN("pxa25x-pwm.0", NULL, PWM0, 1, 1, 0),
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PXA25X_OSC3_CKEN("pxa25x-pwm.1", NULL, PWM1, 1, 1, 0),
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PXA25X_CKEN_1RATE("pxa2xx-fb", NULL, LCD, clk_pxa25x_memory_parents, 0),
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PXA25X_CKEN_1RATE_AO("pxa2xx-pcmcia", NULL, MEMC,
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clk_pxa25x_memory_parents, 0),
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};
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/*
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* In this table, PXA25x_CCCR(N2, M, L) has the following meaning, where :
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* - freq_cpll = n * m * L * 3.6864 MHz
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* - n = N2 / 2
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* - m = 2^(M - 1), where 1 <= M <= 3
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* - l = L_clk_mult[L], ie. { 0, 27, 32, 36, 40, 45, 0, }[L]
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*/
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static struct pxa2xx_freq pxa25x_freqs[] = {
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/* CPU MEMBUS CCCR DIV2 CCLKCFG */
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{ 99532800, 99500, PXA25x_CCCR(2, 1, 1), 1, PXA25x_CLKCFG(1)},
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{199065600, 99500, PXA25x_CCCR(4, 1, 1), 0, PXA25x_CLKCFG(1)},
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{298598400, 99500, PXA25x_CCCR(3, 2, 1), 0, PXA25x_CLKCFG(1)},
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{398131200, 99500, PXA25x_CCCR(4, 2, 1), 0, PXA25x_CLKCFG(1)},
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};
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static u8 clk_pxa25x_core_get_parent(struct clk_hw *hw)
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{
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unsigned long clkcfg;
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unsigned int t;
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asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg));
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t = clkcfg & (1 << 0);
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if (t)
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return PXA_CORE_TURBO;
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return PXA_CORE_RUN;
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}
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static int clk_pxa25x_core_set_parent(struct clk_hw *hw, u8 index)
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{
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if (index > PXA_CORE_TURBO)
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return -EINVAL;
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pxa2xx_core_turbo_switch(index == PXA_CORE_TURBO);
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return 0;
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}
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static int clk_pxa25x_core_determine_rate(struct clk_hw *hw,
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struct clk_rate_request *req)
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{
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return __clk_mux_determine_rate(hw, req);
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}
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PARENTS(clk_pxa25x_core) = { "run", "cpll" };
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MUX_OPS(clk_pxa25x_core, "core", CLK_SET_RATE_PARENT);
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static unsigned long clk_pxa25x_run_get_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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unsigned long cccr = readl(clk_regs + CCCR);
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unsigned int n2 = N2_clk_mult[(cccr >> 7) & 0x07];
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return (parent_rate / n2) * 2;
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}
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PARENTS(clk_pxa25x_run) = { "cpll" };
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RATE_RO_OPS(clk_pxa25x_run, "run");
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static unsigned long clk_pxa25x_cpll_get_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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unsigned long clkcfg, cccr = readl(clk_regs + CCCR);
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unsigned int l, m, n2, t;
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asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg));
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t = clkcfg & (1 << 0);
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l = L_clk_mult[(cccr >> 0) & 0x1f];
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m = M_clk_mult[(cccr >> 5) & 0x03];
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n2 = N2_clk_mult[(cccr >> 7) & 0x07];
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return m * l * n2 * parent_rate / 2;
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}
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static int clk_pxa25x_cpll_determine_rate(struct clk_hw *hw,
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struct clk_rate_request *req)
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{
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return pxa2xx_determine_rate(req, pxa25x_freqs,
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ARRAY_SIZE(pxa25x_freqs));
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}
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static int clk_pxa25x_cpll_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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int i;
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pr_debug("%s(rate=%lu parent_rate=%lu)\n", __func__, rate, parent_rate);
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for (i = 0; i < ARRAY_SIZE(pxa25x_freqs); i++)
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if (pxa25x_freqs[i].cpll == rate)
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break;
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if (i >= ARRAY_SIZE(pxa25x_freqs))
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return -EINVAL;
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pxa2xx_cpll_change(&pxa25x_freqs[i], mdrefr_dri, clk_regs + CCCR);
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return 0;
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}
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PARENTS(clk_pxa25x_cpll) = { "osc_3_6864mhz" };
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RATE_OPS(clk_pxa25x_cpll, "cpll");
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static void __init pxa25x_register_core(void)
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{
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clkdev_pxa_register(CLK_NONE, "cpll", NULL,
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clk_register_clk_pxa25x_cpll());
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clkdev_pxa_register(CLK_NONE, "run", NULL,
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clk_register_clk_pxa25x_run());
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clkdev_pxa_register(CLK_CORE, "core", NULL,
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clk_register_clk_pxa25x_core());
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}
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static void __init pxa25x_register_plls(void)
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{
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clk_register_fixed_rate(NULL, "osc_3_6864mhz", NULL,
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CLK_GET_RATE_NOCACHE, 3686400);
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clkdev_pxa_register(CLK_OSC32k768, "osc_32_768khz", NULL,
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clk_register_fixed_rate(NULL, "osc_32_768khz", NULL,
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CLK_GET_RATE_NOCACHE,
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32768));
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clk_register_fixed_rate(NULL, "clk_dummy", NULL, 0, 0);
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clk_register_fixed_factor(NULL, "ppll_95_85mhz", "osc_3_6864mhz",
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0, 26, 1);
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clk_register_fixed_factor(NULL, "ppll_147_46mhz", "osc_3_6864mhz",
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0, 40, 1);
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}
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static void __init pxa25x_base_clocks_init(void)
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{
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pxa25x_register_plls();
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pxa25x_register_core();
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clkdev_pxa_register(CLK_NONE, "system_bus", NULL,
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clk_register_clk_pxa25x_memory());
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}
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#define DUMMY_CLK(_con_id, _dev_id, _parent) \
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{ .con_id = _con_id, .dev_id = _dev_id, .parent = _parent }
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struct dummy_clk {
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const char *con_id;
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const char *dev_id;
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const char *parent;
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};
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static struct dummy_clk dummy_clks[] __initdata = {
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DUMMY_CLK(NULL, "pxa25x-gpio", "osc_32_768khz"),
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DUMMY_CLK(NULL, "pxa26x-gpio", "osc_32_768khz"),
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DUMMY_CLK("GPIO11_CLK", NULL, "osc_3_6864mhz"),
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DUMMY_CLK("GPIO12_CLK", NULL, "osc_32_768khz"),
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DUMMY_CLK(NULL, "sa1100-rtc", "osc_32_768khz"),
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DUMMY_CLK("OSTIMER0", NULL, "osc_3_6864mhz"),
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DUMMY_CLK("UARTCLK", "pxa2xx-ir", "STUART"),
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};
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static void __init pxa25x_dummy_clocks_init(void)
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{
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struct clk *clk;
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struct dummy_clk *d;
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const char *name;
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int i;
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/*
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* All pinctrl logic has been wiped out of the clock driver, especially
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* for gpio11 and gpio12 outputs. Machine code should ensure proper pin
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* control (ie. pxa2xx_mfp_config() invocation).
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*/
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for (i = 0; i < ARRAY_SIZE(dummy_clks); i++) {
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d = &dummy_clks[i];
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name = d->dev_id ? d->dev_id : d->con_id;
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clk = clk_register_fixed_factor(NULL, name, d->parent, 0, 1, 1);
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clk_register_clkdev(clk, d->con_id, d->dev_id);
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}
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}
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int __init pxa25x_clocks_init(void __iomem *regs)
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{
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clk_regs = regs;
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pxa25x_base_clocks_init();
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pxa25x_dummy_clocks_init();
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return clk_pxa_cken_init(pxa25x_clocks, ARRAY_SIZE(pxa25x_clocks), clk_regs);
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}
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static void __init pxa25x_dt_clocks_init(struct device_node *np)
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{
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pxa25x_clocks_init(ioremap(0x41300000ul, 0x10));
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clk_pxa_dt_common_init(np);
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}
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CLK_OF_DECLARE(pxa25x_clks, "marvell,pxa250-core-clocks",
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pxa25x_dt_clocks_init);
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