131 lines
4.0 KiB
C
131 lines
4.0 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2016 Amlogic, Inc.
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* Author: Michael Turquette <mturquette@baylibre.com>
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*
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* Copyright (c) 2018 Amlogic, inc.
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* Author: Qiufang Dai <qiufang.dai@amlogic.com>
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* Author: Jian Hu <jian.hu@amlogic.com>
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*
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*/
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#ifndef __G12A_H
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#define __G12A_H
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/*
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* Clock controller register offsets
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*
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* Register offsets from the data sheet must be multiplied by 4 before
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* adding them to the base address to get the right value.
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*/
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#define HHI_MIPI_CNTL0 0x000
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#define HHI_MIPI_CNTL1 0x004
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#define HHI_MIPI_CNTL2 0x008
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#define HHI_MIPI_STS 0x00C
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#define HHI_GP0_PLL_CNTL0 0x040
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#define HHI_GP0_PLL_CNTL1 0x044
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#define HHI_GP0_PLL_CNTL2 0x048
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#define HHI_GP0_PLL_CNTL3 0x04C
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#define HHI_GP0_PLL_CNTL4 0x050
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#define HHI_GP0_PLL_CNTL5 0x054
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#define HHI_GP0_PLL_CNTL6 0x058
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#define HHI_GP0_PLL_STS 0x05C
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#define HHI_GP1_PLL_CNTL0 0x060
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#define HHI_GP1_PLL_CNTL1 0x064
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#define HHI_GP1_PLL_CNTL2 0x068
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#define HHI_GP1_PLL_CNTL3 0x06C
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#define HHI_GP1_PLL_CNTL4 0x070
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#define HHI_GP1_PLL_CNTL5 0x074
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#define HHI_GP1_PLL_CNTL6 0x078
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#define HHI_GP1_PLL_STS 0x07C
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#define HHI_PCIE_PLL_CNTL0 0x098
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#define HHI_PCIE_PLL_CNTL1 0x09C
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#define HHI_PCIE_PLL_CNTL2 0x0A0
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#define HHI_PCIE_PLL_CNTL3 0x0A4
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#define HHI_PCIE_PLL_CNTL4 0x0A8
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#define HHI_PCIE_PLL_CNTL5 0x0AC
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#define HHI_PCIE_PLL_STS 0x0B8
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#define HHI_HIFI_PLL_CNTL0 0x0D8
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#define HHI_HIFI_PLL_CNTL1 0x0DC
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#define HHI_HIFI_PLL_CNTL2 0x0E0
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#define HHI_HIFI_PLL_CNTL3 0x0E4
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#define HHI_HIFI_PLL_CNTL4 0x0E8
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#define HHI_HIFI_PLL_CNTL5 0x0EC
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#define HHI_HIFI_PLL_CNTL6 0x0F0
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#define HHI_VIID_CLK_DIV 0x128
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#define HHI_VIID_CLK_CNTL 0x12C
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#define HHI_GCLK_MPEG0 0x140
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#define HHI_GCLK_MPEG1 0x144
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#define HHI_GCLK_MPEG2 0x148
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#define HHI_GCLK_OTHER 0x150
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#define HHI_GCLK_OTHER2 0x154
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#define HHI_SYS_CPU_CLK_CNTL1 0x15c
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#define HHI_VID_CLK_DIV 0x164
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#define HHI_MPEG_CLK_CNTL 0x174
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#define HHI_AUD_CLK_CNTL 0x178
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#define HHI_VID_CLK_CNTL 0x17c
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#define HHI_TS_CLK_CNTL 0x190
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#define HHI_VID_CLK_CNTL2 0x194
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#define HHI_SYS_CPU_CLK_CNTL0 0x19c
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#define HHI_VID_PLL_CLK_DIV 0x1A0
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#define HHI_MALI_CLK_CNTL 0x1b0
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#define HHI_VPU_CLKC_CNTL 0x1b4
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#define HHI_VPU_CLK_CNTL 0x1bC
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#define HHI_ISP_CLK_CNTL 0x1C0
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#define HHI_NNA_CLK_CNTL 0x1C8
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#define HHI_HDMI_CLK_CNTL 0x1CC
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#define HHI_VDEC_CLK_CNTL 0x1E0
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#define HHI_VDEC2_CLK_CNTL 0x1E4
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#define HHI_VDEC3_CLK_CNTL 0x1E8
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#define HHI_VDEC4_CLK_CNTL 0x1EC
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#define HHI_HDCP22_CLK_CNTL 0x1F0
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#define HHI_VAPBCLK_CNTL 0x1F4
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#define HHI_SYS_CPUB_CLK_CNTL1 0x200
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#define HHI_SYS_CPUB_CLK_CNTL 0x208
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#define HHI_VPU_CLKB_CNTL 0x20C
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#define HHI_SYS_CPU_CLK_CNTL2 0x210
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#define HHI_SYS_CPU_CLK_CNTL3 0x214
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#define HHI_SYS_CPU_CLK_CNTL4 0x218
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#define HHI_SYS_CPU_CLK_CNTL5 0x21c
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#define HHI_SYS_CPU_CLK_CNTL6 0x220
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#define HHI_GEN_CLK_CNTL 0x228
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#define HHI_VDIN_MEAS_CLK_CNTL 0x250
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#define HHI_MIPIDSI_PHY_CLK_CNTL 0x254
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#define HHI_NAND_CLK_CNTL 0x25C
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#define HHI_SD_EMMC_CLK_CNTL 0x264
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#define HHI_MPLL_CNTL0 0x278
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#define HHI_MPLL_CNTL1 0x27C
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#define HHI_MPLL_CNTL2 0x280
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#define HHI_MPLL_CNTL3 0x284
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#define HHI_MPLL_CNTL4 0x288
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#define HHI_MPLL_CNTL5 0x28c
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#define HHI_MPLL_CNTL6 0x290
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#define HHI_MPLL_CNTL7 0x294
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#define HHI_MPLL_CNTL8 0x298
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#define HHI_FIX_PLL_CNTL0 0x2A0
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#define HHI_FIX_PLL_CNTL1 0x2A4
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#define HHI_FIX_PLL_CNTL3 0x2AC
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#define HHI_SYS_PLL_CNTL0 0x2f4
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#define HHI_SYS_PLL_CNTL1 0x2f8
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#define HHI_SYS_PLL_CNTL2 0x2fc
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#define HHI_SYS_PLL_CNTL3 0x300
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#define HHI_SYS_PLL_CNTL4 0x304
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#define HHI_SYS_PLL_CNTL5 0x308
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#define HHI_SYS_PLL_CNTL6 0x30c
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#define HHI_HDMI_PLL_CNTL0 0x320
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#define HHI_HDMI_PLL_CNTL1 0x324
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#define HHI_HDMI_PLL_CNTL2 0x328
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#define HHI_HDMI_PLL_CNTL3 0x32c
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#define HHI_HDMI_PLL_CNTL4 0x330
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#define HHI_HDMI_PLL_CNTL5 0x334
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#define HHI_HDMI_PLL_CNTL6 0x338
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#define HHI_SPICC_CLK_CNTL 0x3dc
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#define HHI_SYS1_PLL_CNTL0 0x380
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#define HHI_SYS1_PLL_CNTL1 0x384
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#define HHI_SYS1_PLL_CNTL2 0x388
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#define HHI_SYS1_PLL_CNTL3 0x38c
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#define HHI_SYS1_PLL_CNTL4 0x390
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#define HHI_SYS1_PLL_CNTL5 0x394
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#define HHI_SYS1_PLL_CNTL6 0x398
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#endif /* __G12A_H */
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