239 lines
7.8 KiB
C
239 lines
7.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef ARCH_X86_KVM_REVERSE_CPUID_H
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#define ARCH_X86_KVM_REVERSE_CPUID_H
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#include <uapi/asm/kvm.h>
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#include <asm/cpufeature.h>
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#include <asm/cpufeatures.h>
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/*
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* Hardware-defined CPUID leafs that are either scattered by the kernel or are
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* unknown to the kernel, but need to be directly used by KVM. Note, these
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* word values conflict with the kernel's "bug" caps, but KVM doesn't use those.
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*/
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enum kvm_only_cpuid_leafs {
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CPUID_12_EAX = NCAPINTS,
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CPUID_7_1_EDX,
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CPUID_8000_0007_EDX,
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CPUID_8000_0022_EAX,
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CPUID_7_2_EDX,
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NR_KVM_CPU_CAPS,
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NKVMCAPINTS = NR_KVM_CPU_CAPS - NCAPINTS,
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};
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/*
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* Define a KVM-only feature flag.
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*
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* For features that are scattered by cpufeatures.h, __feature_translate() also
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* needs to be updated to translate the kernel-defined feature into the
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* KVM-defined feature.
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*
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* For features that are 100% KVM-only, i.e. not defined by cpufeatures.h,
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* forego the intermediate KVM_X86_FEATURE and directly define X86_FEATURE_* so
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* that X86_FEATURE_* can be used in KVM. No __feature_translate() handling is
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* needed in this case.
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*/
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#define KVM_X86_FEATURE(w, f) ((w)*32 + (f))
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/* Intel-defined SGX sub-features, CPUID level 0x12 (EAX). */
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#define KVM_X86_FEATURE_SGX1 KVM_X86_FEATURE(CPUID_12_EAX, 0)
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#define KVM_X86_FEATURE_SGX2 KVM_X86_FEATURE(CPUID_12_EAX, 1)
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#define KVM_X86_FEATURE_SGX_EDECCSSA KVM_X86_FEATURE(CPUID_12_EAX, 11)
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/* Intel-defined sub-features, CPUID level 0x00000007:1 (EDX) */
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#define X86_FEATURE_AVX_VNNI_INT8 KVM_X86_FEATURE(CPUID_7_1_EDX, 4)
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#define X86_FEATURE_AVX_NE_CONVERT KVM_X86_FEATURE(CPUID_7_1_EDX, 5)
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#define X86_FEATURE_AMX_COMPLEX KVM_X86_FEATURE(CPUID_7_1_EDX, 8)
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#define X86_FEATURE_PREFETCHITI KVM_X86_FEATURE(CPUID_7_1_EDX, 14)
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/* Intel-defined sub-features, CPUID level 0x00000007:2 (EDX) */
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#define X86_FEATURE_INTEL_PSFD KVM_X86_FEATURE(CPUID_7_2_EDX, 0)
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#define X86_FEATURE_IPRED_CTRL KVM_X86_FEATURE(CPUID_7_2_EDX, 1)
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#define KVM_X86_FEATURE_RRSBA_CTRL KVM_X86_FEATURE(CPUID_7_2_EDX, 2)
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#define X86_FEATURE_DDPD_U KVM_X86_FEATURE(CPUID_7_2_EDX, 3)
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#define KVM_X86_FEATURE_BHI_CTRL KVM_X86_FEATURE(CPUID_7_2_EDX, 4)
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#define X86_FEATURE_MCDT_NO KVM_X86_FEATURE(CPUID_7_2_EDX, 5)
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/* CPUID level 0x80000007 (EDX). */
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#define KVM_X86_FEATURE_CONSTANT_TSC KVM_X86_FEATURE(CPUID_8000_0007_EDX, 8)
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/* CPUID level 0x80000022 (EAX) */
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#define KVM_X86_FEATURE_PERFMON_V2 KVM_X86_FEATURE(CPUID_8000_0022_EAX, 0)
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struct cpuid_reg {
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u32 function;
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u32 index;
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int reg;
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};
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static const struct cpuid_reg reverse_cpuid[] = {
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[CPUID_1_EDX] = { 1, 0, CPUID_EDX},
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[CPUID_8000_0001_EDX] = {0x80000001, 0, CPUID_EDX},
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[CPUID_8086_0001_EDX] = {0x80860001, 0, CPUID_EDX},
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[CPUID_1_ECX] = { 1, 0, CPUID_ECX},
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[CPUID_C000_0001_EDX] = {0xc0000001, 0, CPUID_EDX},
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[CPUID_8000_0001_ECX] = {0x80000001, 0, CPUID_ECX},
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[CPUID_7_0_EBX] = { 7, 0, CPUID_EBX},
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[CPUID_D_1_EAX] = { 0xd, 1, CPUID_EAX},
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[CPUID_8000_0008_EBX] = {0x80000008, 0, CPUID_EBX},
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[CPUID_6_EAX] = { 6, 0, CPUID_EAX},
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[CPUID_8000_000A_EDX] = {0x8000000a, 0, CPUID_EDX},
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[CPUID_7_ECX] = { 7, 0, CPUID_ECX},
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[CPUID_8000_0007_EBX] = {0x80000007, 0, CPUID_EBX},
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[CPUID_7_EDX] = { 7, 0, CPUID_EDX},
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[CPUID_7_1_EAX] = { 7, 1, CPUID_EAX},
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[CPUID_12_EAX] = {0x00000012, 0, CPUID_EAX},
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[CPUID_8000_001F_EAX] = {0x8000001f, 0, CPUID_EAX},
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[CPUID_7_1_EDX] = { 7, 1, CPUID_EDX},
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[CPUID_8000_0007_EDX] = {0x80000007, 0, CPUID_EDX},
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[CPUID_8000_0021_EAX] = {0x80000021, 0, CPUID_EAX},
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[CPUID_8000_0022_EAX] = {0x80000022, 0, CPUID_EAX},
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[CPUID_7_2_EDX] = { 7, 2, CPUID_EDX},
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};
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/*
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* Reverse CPUID and its derivatives can only be used for hardware-defined
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* feature words, i.e. words whose bits directly correspond to a CPUID leaf.
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* Retrieving a feature bit or masking guest CPUID from a Linux-defined word
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* is nonsensical as the bit number/mask is an arbitrary software-defined value
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* and can't be used by KVM to query/control guest capabilities. And obviously
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* the leaf being queried must have an entry in the lookup table.
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*/
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static __always_inline void reverse_cpuid_check(unsigned int x86_leaf)
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{
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BUILD_BUG_ON(NR_CPUID_WORDS != NCAPINTS);
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BUILD_BUG_ON(x86_leaf == CPUID_LNX_1);
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BUILD_BUG_ON(x86_leaf == CPUID_LNX_2);
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BUILD_BUG_ON(x86_leaf == CPUID_LNX_3);
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BUILD_BUG_ON(x86_leaf == CPUID_LNX_4);
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BUILD_BUG_ON(x86_leaf == CPUID_LNX_5);
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BUILD_BUG_ON(x86_leaf >= ARRAY_SIZE(reverse_cpuid));
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BUILD_BUG_ON(reverse_cpuid[x86_leaf].function == 0);
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}
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/*
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* Translate feature bits that are scattered in the kernel's cpufeatures word
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* into KVM feature words that align with hardware's definitions.
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*/
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static __always_inline u32 __feature_translate(int x86_feature)
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{
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#define KVM_X86_TRANSLATE_FEATURE(f) \
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case X86_FEATURE_##f: return KVM_X86_FEATURE_##f
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switch (x86_feature) {
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KVM_X86_TRANSLATE_FEATURE(SGX1);
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KVM_X86_TRANSLATE_FEATURE(SGX2);
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KVM_X86_TRANSLATE_FEATURE(SGX_EDECCSSA);
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KVM_X86_TRANSLATE_FEATURE(CONSTANT_TSC);
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KVM_X86_TRANSLATE_FEATURE(PERFMON_V2);
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KVM_X86_TRANSLATE_FEATURE(RRSBA_CTRL);
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KVM_X86_TRANSLATE_FEATURE(BHI_CTRL);
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default:
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return x86_feature;
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}
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}
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static __always_inline u32 __feature_leaf(int x86_feature)
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{
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return __feature_translate(x86_feature) / 32;
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}
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/*
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* Retrieve the bit mask from an X86_FEATURE_* definition. Features contain
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* the hardware defined bit number (stored in bits 4:0) and a software defined
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* "word" (stored in bits 31:5). The word is used to index into arrays of
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* bit masks that hold the per-cpu feature capabilities, e.g. this_cpu_has().
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*/
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static __always_inline u32 __feature_bit(int x86_feature)
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{
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x86_feature = __feature_translate(x86_feature);
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reverse_cpuid_check(x86_feature / 32);
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return 1 << (x86_feature & 31);
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}
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#define feature_bit(name) __feature_bit(X86_FEATURE_##name)
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static __always_inline struct cpuid_reg x86_feature_cpuid(unsigned int x86_feature)
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{
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unsigned int x86_leaf = __feature_leaf(x86_feature);
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reverse_cpuid_check(x86_leaf);
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return reverse_cpuid[x86_leaf];
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}
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static __always_inline u32 *__cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry,
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u32 reg)
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{
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switch (reg) {
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case CPUID_EAX:
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return &entry->eax;
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case CPUID_EBX:
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return &entry->ebx;
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case CPUID_ECX:
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return &entry->ecx;
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case CPUID_EDX:
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return &entry->edx;
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default:
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BUILD_BUG();
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return NULL;
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}
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}
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static __always_inline u32 *cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry,
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unsigned int x86_feature)
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{
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const struct cpuid_reg cpuid = x86_feature_cpuid(x86_feature);
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return __cpuid_entry_get_reg(entry, cpuid.reg);
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}
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static __always_inline u32 cpuid_entry_get(struct kvm_cpuid_entry2 *entry,
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unsigned int x86_feature)
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{
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u32 *reg = cpuid_entry_get_reg(entry, x86_feature);
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return *reg & __feature_bit(x86_feature);
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}
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static __always_inline bool cpuid_entry_has(struct kvm_cpuid_entry2 *entry,
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unsigned int x86_feature)
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{
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return cpuid_entry_get(entry, x86_feature);
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}
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static __always_inline void cpuid_entry_clear(struct kvm_cpuid_entry2 *entry,
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unsigned int x86_feature)
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{
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u32 *reg = cpuid_entry_get_reg(entry, x86_feature);
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*reg &= ~__feature_bit(x86_feature);
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}
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static __always_inline void cpuid_entry_set(struct kvm_cpuid_entry2 *entry,
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unsigned int x86_feature)
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{
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u32 *reg = cpuid_entry_get_reg(entry, x86_feature);
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*reg |= __feature_bit(x86_feature);
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}
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static __always_inline void cpuid_entry_change(struct kvm_cpuid_entry2 *entry,
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unsigned int x86_feature,
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bool set)
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{
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u32 *reg = cpuid_entry_get_reg(entry, x86_feature);
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/*
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* Open coded instead of using cpuid_entry_{clear,set}() to coerce the
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* compiler into using CMOV instead of Jcc when possible.
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*/
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if (set)
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*reg |= __feature_bit(x86_feature);
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else
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*reg &= ~__feature_bit(x86_feature);
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}
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#endif /* ARCH_X86_KVM_REVERSE_CPUID_H */
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