296 lines
8.1 KiB
C
296 lines
8.1 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* linux/arch/alpha/kernel/sys_miata.c
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*
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* Copyright (C) 1995 David A Rusling
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* Copyright (C) 1996 Jay A Estabrook
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* Copyright (C) 1998, 1999, 2000 Richard Henderson
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*
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* Code supporting the MIATA (EV56+PYXIS).
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/mm.h>
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#include <linux/sched.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/reboot.h>
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#include <asm/ptrace.h>
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#include <asm/dma.h>
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#include <asm/irq.h>
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#include <asm/mmu_context.h>
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#include <asm/io.h>
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#include <asm/core_cia.h>
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#include <asm/tlbflush.h>
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#include "proto.h"
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#include "irq_impl.h"
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#include "pci_impl.h"
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#include "machvec_impl.h"
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static void
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miata_srm_device_interrupt(unsigned long vector)
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{
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int irq;
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irq = (vector - 0x800) >> 4;
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/*
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* I really hate to do this, but the MIATA SRM console ignores the
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* low 8 bits in the interrupt summary register, and reports the
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* vector 0x80 *lower* than I expected from the bit numbering in
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* the documentation.
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* This was done because the low 8 summary bits really aren't used
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* for reporting any interrupts (the PCI-ISA bridge, bit 7, isn't
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* used for this purpose, as PIC interrupts are delivered as the
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* vectors 0x800-0x8f0).
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* But I really don't want to change the fixup code for allocation
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* of IRQs, nor the alpha_irq_mask maintenance stuff, both of which
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* look nice and clean now.
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* So, here's this grotty hack... :-(
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*/
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if (irq >= 16)
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irq = irq + 8;
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handle_irq(irq);
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}
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static void __init
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miata_init_irq(void)
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{
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if (alpha_using_srm)
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alpha_mv.device_interrupt = miata_srm_device_interrupt;
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#if 0
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/* These break on MiataGL so we'll try not to do it at all. */
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*(vulp)PYXIS_INT_HILO = 0x000000B2UL; mb(); /* ISA/NMI HI */
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*(vulp)PYXIS_RT_COUNT = 0UL; mb(); /* clear count */
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#endif
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init_i8259a_irqs();
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/* Not interested in the bogus interrupts (3,10), Fan Fault (0),
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NMI (1), or EIDE (9).
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We also disable the risers (4,5), since we don't know how to
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route the interrupts behind the bridge. */
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init_pyxis_irqs(0x63b0000);
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common_init_isa_dma();
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if (request_irq(16 + 2, no_action, 0, "halt-switch", NULL))
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pr_err("Failed to register halt-switch interrupt\n");
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if (request_irq(16 + 6, no_action, 0, "timer-cascade", NULL))
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pr_err("Failed to register timer-cascade interrupt\n");
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}
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/*
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* PCI Fixup configuration.
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*
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* Summary @ PYXIS_INT_REQ:
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* Bit Meaning
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* 0 Fan Fault
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* 1 NMI
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* 2 Halt/Reset switch
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* 3 none
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* 4 CID0 (Riser ID)
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* 5 CID1 (Riser ID)
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* 6 Interval timer
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* 7 PCI-ISA Bridge
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* 8 Ethernet
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* 9 EIDE (deprecated, ISA 14/15 used)
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*10 none
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*11 USB
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*12 Interrupt Line A from slot 4
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*13 Interrupt Line B from slot 4
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*14 Interrupt Line C from slot 4
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*15 Interrupt Line D from slot 4
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*16 Interrupt Line A from slot 5
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*17 Interrupt line B from slot 5
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*18 Interrupt Line C from slot 5
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*19 Interrupt Line D from slot 5
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*20 Interrupt Line A from slot 1
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*21 Interrupt Line B from slot 1
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*22 Interrupt Line C from slot 1
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*23 Interrupt Line D from slot 1
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*24 Interrupt Line A from slot 2
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*25 Interrupt Line B from slot 2
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*26 Interrupt Line C from slot 2
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*27 Interrupt Line D from slot 2
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*27 Interrupt Line A from slot 3
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*29 Interrupt Line B from slot 3
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*30 Interrupt Line C from slot 3
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*31 Interrupt Line D from slot 3
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*
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* The device to slot mapping looks like:
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*
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* Slot Device
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* 3 DC21142 Ethernet
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* 4 EIDE CMD646
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* 5 none
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* 6 USB
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* 7 PCI-ISA bridge
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* 8 PCI-PCI Bridge (SBU Riser)
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* 9 none
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* 10 none
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* 11 PCI on board slot 4 (SBU Riser)
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* 12 PCI on board slot 5 (SBU Riser)
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*
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* These are behind the bridge, so I'm not sure what to do...
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*
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* 13 PCI on board slot 1 (SBU Riser)
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* 14 PCI on board slot 2 (SBU Riser)
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* 15 PCI on board slot 3 (SBU Riser)
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*
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*
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* This two layered interrupt approach means that we allocate IRQ 16 and
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* above for PCI interrupts. The IRQ relates to which bit the interrupt
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* comes in on. This makes interrupt processing much easier.
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*/
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static int
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miata_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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{
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static char irq_tab[18][5] = {
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/*INT INTA INTB INTC INTD */
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{16+ 8, 16+ 8, 16+ 8, 16+ 8, 16+ 8}, /* IdSel 14, DC21142 */
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{ -1, -1, -1, -1, -1}, /* IdSel 15, EIDE */
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{ -1, -1, -1, -1, -1}, /* IdSel 16, none */
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{ -1, -1, -1, -1, -1}, /* IdSel 17, none */
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{ -1, -1, -1, -1, -1}, /* IdSel 18, PCI-ISA */
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{ -1, -1, -1, -1, -1}, /* IdSel 19, PCI-PCI */
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{ -1, -1, -1, -1, -1}, /* IdSel 20, none */
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{ -1, -1, -1, -1, -1}, /* IdSel 21, none */
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{16+12, 16+12, 16+13, 16+14, 16+15}, /* IdSel 22, slot 4 */
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{16+16, 16+16, 16+17, 16+18, 16+19}, /* IdSel 23, slot 5 */
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/* the next 7 are actually on PCI bus 1, across the bridge */
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{16+11, 16+11, 16+11, 16+11, 16+11}, /* IdSel 24, QLISP/GL*/
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{ -1, -1, -1, -1, -1}, /* IdSel 25, none */
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{ -1, -1, -1, -1, -1}, /* IdSel 26, none */
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{ -1, -1, -1, -1, -1}, /* IdSel 27, none */
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{16+20, 16+20, 16+21, 16+22, 16+23}, /* IdSel 28, slot 1 */
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{16+24, 16+24, 16+25, 16+26, 16+27}, /* IdSel 29, slot 2 */
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{16+28, 16+28, 16+29, 16+30, 16+31}, /* IdSel 30, slot 3 */
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/* This bridge is on the main bus of the later orig MIATA */
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{ -1, -1, -1, -1, -1}, /* IdSel 31, PCI-PCI */
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};
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const long min_idsel = 3, max_idsel = 20, irqs_per_slot = 5;
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/* the USB function of the 82c693 has it's interrupt connected to
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the 2nd 8259 controller. So we have to check for it first. */
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if((slot == 7) && (PCI_FUNC(dev->devfn) == 3)) {
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struct pci_dev *pdev = pci_get_slot(dev->bus, dev->devfn & ~7);
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u8 irq = 0;
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int ret;
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if (!pdev)
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return -1;
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ret = pci_read_config_byte(pdev, 0x40, &irq);
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pci_dev_put(pdev);
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return ret == PCIBIOS_SUCCESSFUL ? irq : -1;
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}
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return COMMON_TABLE_LOOKUP;
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}
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static u8
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miata_swizzle(struct pci_dev *dev, u8 *pinp)
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{
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int slot, pin = *pinp;
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if (dev->bus->number == 0) {
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slot = PCI_SLOT(dev->devfn);
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}
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/* Check for the built-in bridge. */
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else if ((PCI_SLOT(dev->bus->self->devfn) == 8) ||
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(PCI_SLOT(dev->bus->self->devfn) == 20)) {
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slot = PCI_SLOT(dev->devfn) + 9;
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}
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else
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{
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/* Must be a card-based bridge. */
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do {
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if ((PCI_SLOT(dev->bus->self->devfn) == 8) ||
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(PCI_SLOT(dev->bus->self->devfn) == 20)) {
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slot = PCI_SLOT(dev->devfn) + 9;
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break;
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}
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pin = pci_swizzle_interrupt_pin(dev, pin);
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/* Move up the chain of bridges. */
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dev = dev->bus->self;
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/* Slot of the next bridge. */
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slot = PCI_SLOT(dev->devfn);
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} while (dev->bus->self);
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}
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*pinp = pin;
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return slot;
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}
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static void __init
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miata_init_pci(void)
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{
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cia_init_pci();
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SMC669_Init(0); /* it might be a GL (fails harmlessly if not) */
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es1888_init();
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}
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static void
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miata_kill_arch(int mode)
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{
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cia_kill_arch(mode);
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#ifndef ALPHA_RESTORE_SRM_SETUP
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switch(mode) {
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case LINUX_REBOOT_CMD_RESTART:
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/* Who said DEC engineers have no sense of humor? ;-) */
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if (alpha_using_srm) {
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*(vuip) PYXIS_RESET = 0x0000dead;
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mb();
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}
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break;
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case LINUX_REBOOT_CMD_HALT:
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break;
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case LINUX_REBOOT_CMD_POWER_OFF:
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break;
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}
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halt();
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#endif
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}
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/*
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* The System Vector
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*/
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struct alpha_machine_vector miata_mv __initmv = {
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.vector_name = "Miata",
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DO_EV5_MMU,
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DO_DEFAULT_RTC,
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DO_PYXIS_IO,
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.machine_check = cia_machine_check,
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.max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
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.min_io_address = DEFAULT_IO_BASE,
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.min_mem_address = DEFAULT_MEM_BASE,
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.pci_dac_offset = PYXIS_DAC_OFFSET,
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.nr_irqs = 48,
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.device_interrupt = pyxis_device_interrupt,
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.init_arch = pyxis_init_arch,
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.init_irq = miata_init_irq,
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.init_rtc = common_init_rtc,
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.init_pci = miata_init_pci,
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.kill_arch = miata_kill_arch,
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.pci_map_irq = miata_map_irq,
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.pci_swizzle = miata_swizzle,
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};
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ALIAS_MV(miata)
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