72 lines
1.6 KiB
YAML
72 lines
1.6 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/watchdog/starfive,jh7100-wdt.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: StarFive Watchdog for JH7100 and JH7110 SoC
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maintainers:
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- Xingyu Wu <xingyu.wu@starfivetech.com>
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- Samin Guo <samin.guo@starfivetech.com>
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description:
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The JH7100 and JH7110 watchdog both are 32 bit counters. JH7100 watchdog
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has only one timeout phase and reboots. And JH7110 watchdog has two
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timeout phases. At the first phase, the signal of watchdog interrupt
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output(WDOGINT) will rise when counter is 0. The counter will reload
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the timeout value. And then, if counter decreases to 0 again and WDOGINT
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isn't cleared, the watchdog will reset the system unless the watchdog
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reset is disabled.
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allOf:
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- $ref: watchdog.yaml#
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properties:
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compatible:
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enum:
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- starfive,jh7100-wdt
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- starfive,jh7110-wdt
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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items:
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- description: APB clock
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- description: Core clock
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clock-names:
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items:
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- const: apb
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- const: core
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resets:
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items:
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- description: APB reset
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- description: Core reset
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- resets
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unevaluatedProperties: false
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examples:
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- |
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watchdog@12480000 {
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compatible = "starfive,jh7100-wdt";
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reg = <0x12480000 0x10000>;
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clocks = <&clk 171>,
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<&clk 172>;
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clock-names = "apb", "core";
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resets = <&rst 99>,
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<&rst 100>;
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};
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