81 lines
2.0 KiB
YAML
81 lines
2.0 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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# Copyright 2023 Realtek Semiconductor Corporation
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/usb/realtek,rtd-dwc3.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Realtek DWC3 USB SoC Controller Glue
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maintainers:
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- Stanley Chang <stanley_chang@realtek.com>
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description:
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The Realtek DHC SoC embeds a DWC3 USB IP Core configured for USB 2.0
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and USB 3.0 in host or dual-role mode.
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properties:
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compatible:
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items:
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- enum:
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- realtek,rtd1295-dwc3
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- realtek,rtd1315e-dwc3
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- realtek,rtd1319-dwc3
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- realtek,rtd1319d-dwc3
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- realtek,rtd1395-dwc3
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- realtek,rtd1619-dwc3
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- realtek,rtd1619b-dwc3
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- const: realtek,rtd-dwc3
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reg:
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items:
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- description: Address and length of register set for wrapper of dwc3 core.
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- description: Address and length of register set for pm control.
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'#address-cells':
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const: 1
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'#size-cells':
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const: 1
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ranges: true
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patternProperties:
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"^usb@[0-9a-f]+$":
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$ref: snps,dwc3.yaml#
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description: Required child node
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required:
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- compatible
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- reg
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- "#address-cells"
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- "#size-cells"
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- ranges
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additionalProperties: false
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examples:
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- |
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usb@98013e00 {
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compatible = "realtek,rtd1319d-dwc3", "realtek,rtd-dwc3";
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reg = <0x98013e00 0x140>, <0x98013f60 0x4>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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usb@98050000 {
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compatible = "snps,dwc3";
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reg = <0x98050000 0x9000>;
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interrupts = <0 94 4>;
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phys = <&usb2phy &usb3phy>;
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phy-names = "usb2-phy", "usb3-phy";
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dr_mode = "otg";
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usb-role-switch;
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role-switch-default-mode = "host";
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snps,dis_u2_susphy_quirk;
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snps,parkmode-disable-ss-quirk;
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snps,parkmode-disable-hs-quirk;
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maximum-speed = "high-speed";
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};
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};
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