208 lines
5.0 KiB
YAML
208 lines
5.0 KiB
YAML
# SPDX-License-Identifier: GPL-2.0-only
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/spi/snps,dw-apb-ssi.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Synopsys DesignWare AMBA 2.0 Synchronous Serial Interface
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maintainers:
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- Mark Brown <broonie@kernel.org>
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allOf:
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- $ref: spi-controller.yaml#
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- if:
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properties:
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compatible:
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contains:
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enum:
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- mscc,ocelot-spi
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- mscc,jaguar2-spi
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then:
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properties:
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reg:
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minItems: 2
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- if:
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properties:
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compatible:
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contains:
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enum:
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- baikal,bt1-sys-ssi
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then:
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properties:
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mux-controls:
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maxItems: 1
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required:
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- mux-controls
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else:
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required:
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- interrupts
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- if:
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properties:
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compatible:
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contains:
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const: amd,pensando-elba-spi
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then:
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required:
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- amd,pensando-elba-syscon
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else:
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properties:
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amd,pensando-elba-syscon: false
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properties:
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compatible:
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oneOf:
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- description: Generic DW SPI Controller
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enum:
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- snps,dw-apb-ssi
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- snps,dwc-ssi-1.01a
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- description: Microsemi Ocelot/Jaguar2 SoC SPI Controller
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items:
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- enum:
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- mscc,ocelot-spi
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- mscc,jaguar2-spi
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- const: snps,dw-apb-ssi
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- description: Microchip Sparx5 SoC SPI Controller
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const: microchip,sparx5-spi
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- description: Amazon Alpine SPI Controller
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const: amazon,alpine-dw-apb-ssi
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- description: Renesas RZ/N1 SPI Controller
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items:
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- const: renesas,rzn1-spi
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- const: snps,dw-apb-ssi
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- description: Intel Keem Bay SPI Controller
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const: intel,keembay-ssi
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- description: Intel Mount Evans Integrated Management Complex SPI Controller
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const: intel,mountevans-imc-ssi
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- description: AMD Pensando Elba SoC SPI Controller
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const: amd,pensando-elba-spi
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- description: Baikal-T1 SPI Controller
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const: baikal,bt1-ssi
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- description: Baikal-T1 System Boot SPI Controller
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const: baikal,bt1-sys-ssi
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- description: Canaan Kendryte K210 SoS SPI Controller
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const: canaan,k210-spi
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- description: Renesas RZ/N1 SPI Controller
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items:
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- enum:
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- renesas,r9a06g032-spi # RZ/N1D
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- renesas,r9a06g033-spi # RZ/N1S
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- const: renesas,rzn1-spi # RZ/N1
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reg:
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minItems: 1
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items:
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- description: DW APB SSI controller memory mapped registers
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- description: SPI MST region map or directly mapped SPI ROM
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interrupts:
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maxItems: 1
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clocks:
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minItems: 1
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items:
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- description: SPI Controller reference clock source
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- description: APB interface clock source
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clock-names:
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minItems: 1
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items:
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- const: ssi_clk
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- const: pclk
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resets:
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maxItems: 1
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reset-names:
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const: spi
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reg-io-width:
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description: I/O register width (in bytes) implemented by this device
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default: 4
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enum: [ 2, 4 ]
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num-cs:
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default: 4
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minimum: 1
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maximum: 4
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dmas:
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items:
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- description: TX DMA Channel
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- description: RX DMA Channel
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dma-names:
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items:
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- const: tx
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- const: rx
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rx-sample-delay-ns:
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default: 0
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description: |
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Default value of the rx-sample-delay-ns property.
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This value will be used if the property is not explicitly defined
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for a SPI slave device.
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SPI Rx sample delay offset, unit is nanoseconds.
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The delay from the default sample time before the actual sample of the
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rxd input signal occurs. The "rx_sample_delay" is an optional feature
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of the designware controller, and the upper limit is also subject to
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controller configuration.
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amd,pensando-elba-syscon:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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description:
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Block address to control SPI chip-selects. The Elba SoC system controller
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provides an interface to override the native DWC SSI CS control.
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patternProperties:
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"^.*@[0-9a-f]+$":
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type: object
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additionalProperties: true
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properties:
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reg:
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minimum: 0
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maximum: 3
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unevaluatedProperties: false
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required:
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- compatible
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- reg
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- "#address-cells"
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- "#size-cells"
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- clocks
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examples:
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- |
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spi@fff00000 {
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compatible = "snps,dw-apb-ssi";
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reg = <0xfff00000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 154 4>;
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clocks = <&spi_m_clk>;
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num-cs = <2>;
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cs-gpios = <&gpio0 13 0>,
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<&gpio0 14 0>;
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rx-sample-delay-ns = <3>;
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flash@1 {
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compatible = "spi-nand";
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reg = <1>;
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rx-sample-delay-ns = <7>;
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};
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};
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- |
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spi@1f040100 {
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compatible = "baikal,bt1-sys-ssi";
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reg = <0x1f040100 0x900>,
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<0x1c000000 0x1000000>;
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#address-cells = <1>;
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#size-cells = <0>;
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mux-controls = <&boot_mux>;
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clocks = <&ccu_sys>;
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clock-names = "ssi_clk";
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};
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...
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