197 lines
6.2 KiB
YAML
197 lines
6.2 KiB
YAML
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/spi/brcm,spi-bcm-qspi.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Broadcom SPI controller
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maintainers:
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- Kamal Dasu <kdasu.kdev@gmail.com>
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- Rafał Miłecki <rafal@milecki.pl>
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description: |
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The Broadcom SPI controller is a SPI master found on various SOCs, including
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BRCMSTB (BCM7XXX), Cygnus, NSP and NS2. The Broadcom Master SPI hw IP consists
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of:
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MSPI : SPI master controller can read and write to a SPI slave device
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BSPI : Broadcom SPI in combination with the MSPI hw IP provides acceleration
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for flash reads and be configured to do single, double, quad lane
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io with 3-byte and 4-byte addressing support.
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Supported Broadcom SoCs have one instance of MSPI+BSPI controller IP.
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MSPI master can be used without BSPI. BRCMSTB SoCs have an additional instance
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of a MSPI master without the BSPI to use with non flash slave devices that
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use SPI protocol.
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allOf:
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- $ref: spi-controller.yaml#
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properties:
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compatible:
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oneOf:
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- description: Second Instance of MSPI BRCMSTB SoCs
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items:
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- enum:
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- brcm,spi-bcm7425-qspi
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- brcm,spi-bcm7429-qspi
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- brcm,spi-bcm7435-qspi
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- brcm,spi-bcm7445-qspi
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- brcm,spi-bcm7216-qspi
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- brcm,spi-bcm7278-qspi
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- const: brcm,spi-bcm-qspi
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- const: brcm,spi-brcmstb-mspi
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- description: Second Instance of MSPI BRCMSTB SoCs
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items:
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- enum:
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- brcm,spi-brcmstb-qspi
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- brcm,spi-brcmstb-mspi
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- brcm,spi-nsp-qspi
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- brcm,spi-ns2-qspi
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- const: brcm,spi-bcm-qspi
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reg:
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minItems: 1
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maxItems: 5
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reg-names:
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minItems: 1
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items:
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- const: mspi
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- const: bspi
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- enum: [ intr_regs, intr_status_reg, cs_reg ]
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- enum: [ intr_regs, intr_status_reg, cs_reg ]
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- enum: [ intr_regs, intr_status_reg, cs_reg ]
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interrupts:
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minItems: 1
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maxItems: 7
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interrupt-names:
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oneOf:
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- minItems: 1
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items:
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- const: mspi_done
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- const: mspi_halted
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- const: spi_lr_fullness_reached
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- const: spi_lr_session_aborted
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- const: spi_lr_impatient
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- const: spi_lr_session_done
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- const: spi_lr_overread
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- const: spi_l1_intr
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clocks:
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maxItems: 1
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description: reference clock for this block
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native-endian:
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$ref: /schemas/types.yaml#/definitions/flag
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description: Defined when using BE SoC and device uses BE register read/write
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unevaluatedProperties: false
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required:
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- reg
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- reg-names
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- interrupts
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- interrupt-names
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examples:
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- | # BRCMSTB SoC: SPI Master (MSPI+BSPI) for SPI-NOR access
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spi@f03e3400 {
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compatible = "brcm,spi-brcmstb-qspi", "brcm,spi-bcm-qspi";
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reg = <0xf03e3400 0x188>, <0xf03e3200 0x50>, <0xf03e0920 0x4>;
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reg-names = "mspi", "bspi", "cs_reg";
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interrupts = <0x5>, <0x6>, <0x1>, <0x2>, <0x3>, <0x4>, <0x0>;
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interrupt-parent = <&gic>;
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interrupt-names = "mspi_done",
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"mspi_halted",
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"spi_lr_fullness_reached",
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"spi_lr_session_aborted",
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"spi_lr_impatient",
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"spi_lr_session_done",
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"spi_lr_overread";
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clocks = <&hif_spi>;
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#address-cells = <0x1>;
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#size-cells = <0x0>;
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flash@0 {
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#size-cells = <0x2>;
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#address-cells = <0x2>;
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compatible = "m25p80";
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reg = <0x0>;
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spi-max-frequency = <0x2625a00>;
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spi-cpol;
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spi-cpha;
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};
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};
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- | # BRCMSTB SoC: MSPI master for any SPI device
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spi@f0416000 {
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clocks = <&upg_fixed>;
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compatible = "brcm,spi-brcmstb-mspi", "brcm,spi-bcm-qspi";
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reg = <0xf0416000 0x180>;
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reg-names = "mspi";
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interrupts = <0x14>;
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interrupt-parent = <&irq0_aon_intc>;
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interrupt-names = "mspi_done";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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- | # iProc SoC
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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spi@18027200 {
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compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi";
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reg = <0x18027200 0x184>,
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<0x18027000 0x124>,
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<0x1811c408 0x004>,
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<0x180273a0 0x01c>;
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reg-names = "mspi", "bspi", "intr_regs", "intr_status_reg";
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interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "mspi_done",
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"mspi_halted",
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"spi_lr_fullness_reached",
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"spi_lr_session_aborted",
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"spi_lr_impatient",
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"spi_lr_session_done";
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clocks = <&iprocmed>;
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num-cs = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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- | # NS2 SoC
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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spi@66470200 {
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compatible = "brcm,spi-ns2-qspi", "brcm,spi-bcm-qspi";
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reg = <0x66470200 0x184>,
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<0x66470000 0x124>,
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<0x67017408 0x004>,
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<0x664703a0 0x01c>;
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reg-names = "mspi", "bspi", "intr_regs", "intr_status_reg";
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interrupts = <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "spi_l1_intr";
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clocks = <&iprocmed>;
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num-cs = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "m25p80";
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reg = <0x0>;
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spi-max-frequency = <12500000>;
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spi-cpol;
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spi-cpha;
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};
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};
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