90 lines
1.9 KiB
YAML
90 lines
1.9 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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# Copyright (C) 2022 Microchip Technology, Inc. and its subsidiaries
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/spi/atmel,at91rm9200-spi.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Atmel SPI device
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maintainers:
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- Tudor Ambarus <tudor.ambarus@linaro.org>
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allOf:
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- $ref: spi-controller.yaml#
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properties:
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compatible:
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oneOf:
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- const: atmel,at91rm9200-spi
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- items:
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- const: microchip,sam9x60-spi
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- const: atmel,at91rm9200-spi
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- items:
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- const: microchip,sam9x7-spi
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- const: microchip,sam9x60-spi
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- const: atmel,at91rm9200-spi
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clock-names:
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contains:
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const: spi_clk
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clocks:
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maxItems: 1
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dmas:
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items:
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- description: TX DMA Channel
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- description: RX DMA Channel
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dma-names:
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items:
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- const: tx
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- const: rx
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atmel,fifo-size:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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Maximum number of data the RX and TX FIFOs can store for FIFO
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capable SPI controllers.
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enum: [ 16, 32 ]
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required:
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- compatible
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- reg
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- interrupts
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- clock-names
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- clocks
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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spi1: spi@fffcc000 {
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compatible = "atmel,at91rm9200-spi";
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reg = <0xfffcc000 0x4000>;
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interrupts = <13 IRQ_TYPE_LEVEL_HIGH 5>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&spi1_clk>;
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clock-names = "spi_clk";
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cs-gpios = <&pioB 3 GPIO_ACTIVE_HIGH>;
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atmel,fifo-size = <32>;
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mmc@0 {
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compatible = "mmc-spi-slot";
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reg = <0>;
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gpios = <&pioC 4 GPIO_ACTIVE_HIGH>; /* CD */
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spi-max-frequency = <25000000>;
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};
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};
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