99 lines
2.5 KiB
YAML
99 lines
2.5 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/phy/ti,phy-am654-serdes.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: TI AM654 SERDES
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description:
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This binding describes the TI AM654 SERDES. AM654 SERDES can be configured
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to be used with either PCIe or USB or SGMII.
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maintainers:
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- Kishon Vijay Abraham I <kishon@ti.com>
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properties:
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compatible:
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enum:
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- ti,phy-am654-serdes
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reg:
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maxItems: 1
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reg-names:
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items:
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- const: serdes
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power-domains:
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maxItems: 1
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clocks:
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maxItems: 3
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description:
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Three input clocks referring to left input reference clock, refclk and right input reference
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clock.
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'#phy-cells':
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const: 2
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description:
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The 1st cell corresponds to the phy type (should be one of the types specified in
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include/dt-bindings/phy/phy.h) and the 2nd cell should be the serdes lane function.
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ti,serdes-clk:
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description: Phandle to the SYSCON entry required for configuring SERDES clock selection.
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$ref: /schemas/types.yaml#/definitions/phandle
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'#clock-cells':
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const: 1
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mux-controls:
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maxItems: 1
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description: Phandle to the SYSCON entry required for configuring SERDES lane function.
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clock-output-names:
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oneOf:
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- description: Clock output names for SERDES 0
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items:
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- const: serdes0_cmu_refclk
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- const: serdes0_lo_refclk
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- const: serdes0_ro_refclk
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- description: Clock output names for SERDES 1
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items:
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- const: serdes1_cmu_refclk
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- const: serdes1_lo_refclk
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- const: serdes1_ro_refclk
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required:
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- compatible
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- reg
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- power-domains
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- clocks
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- assigned-clocks
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- assigned-clock-parents
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- ti,serdes-clk
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- mux-controls
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- clock-output-names
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/phy/phy-am654-serdes.h>
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serdes0: serdes@900000 {
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compatible = "ti,phy-am654-serdes";
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reg = <0x900000 0x2000>;
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reg-names = "serdes";
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#phy-cells = <2>;
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power-domains = <&k3_pds 153>;
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clocks = <&k3_clks 153 4>, <&k3_clks 153 1>,
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<&serdes1 AM654_SERDES_LO_REFCLK>;
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clock-output-names = "serdes0_cmu_refclk", "serdes0_lo_refclk", "serdes0_ro_refclk";
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assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>;
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assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>;
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ti,serdes-clk = <&serdes0_clk>;
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mux-controls = <&serdes_mux 0>;
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#clock-cells = <1>;
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};
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