110 lines
2.5 KiB
YAML
110 lines
2.5 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
|
%YAML 1.2
|
|
---
|
|
$id: http://devicetree.org/schemas/phy/intel,combo-phy.yaml#
|
|
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
|
|
|
title: Intel ComboPhy Subsystem
|
|
|
|
maintainers:
|
|
- Dilip Kota <eswara.kota@linux.intel.com>
|
|
|
|
description: |
|
|
Intel Combophy subsystem supports PHYs for PCIe, EMAC and SATA
|
|
controllers. A single Combophy provides two PHY instances.
|
|
|
|
properties:
|
|
$nodename:
|
|
pattern: "combophy(@.*|-([0-9]|[1-9][0-9]+))?$"
|
|
|
|
compatible:
|
|
items:
|
|
- const: intel,combophy-lgm
|
|
- const: intel,combo-phy
|
|
|
|
clocks:
|
|
maxItems: 1
|
|
|
|
reg:
|
|
items:
|
|
- description: ComboPhy core registers
|
|
- description: PCIe app core control registers
|
|
|
|
reg-names:
|
|
items:
|
|
- const: core
|
|
- const: app
|
|
|
|
resets:
|
|
maxItems: 4
|
|
|
|
reset-names:
|
|
items:
|
|
- const: phy
|
|
- const: core
|
|
- const: iphy0
|
|
- const: iphy1
|
|
|
|
intel,syscfg:
|
|
$ref: /schemas/types.yaml#/definitions/phandle-array
|
|
items:
|
|
- items:
|
|
- description: phandle to Chip configuration registers
|
|
- description: ComboPhy instance id
|
|
description: Chip configuration registers handle and ComboPhy instance id
|
|
|
|
intel,hsio:
|
|
$ref: /schemas/types.yaml#/definitions/phandle-array
|
|
items:
|
|
- items:
|
|
- description: phandle to HSIO registers
|
|
- description: ComboPhy instance id
|
|
description: HSIO registers handle and ComboPhy instance id on NOC
|
|
|
|
intel,aggregation:
|
|
type: boolean
|
|
description: |
|
|
Specify the flag to configure ComboPHY in dual lane mode.
|
|
|
|
intel,phy-mode:
|
|
$ref: /schemas/types.yaml#/definitions/uint32
|
|
description: |
|
|
Mode of the two phys in ComboPhy.
|
|
See dt-bindings/phy/phy.h for values.
|
|
|
|
"#phy-cells":
|
|
const: 1
|
|
|
|
required:
|
|
- compatible
|
|
- clocks
|
|
- reg
|
|
- reg-names
|
|
- intel,syscfg
|
|
- intel,hsio
|
|
- intel,phy-mode
|
|
- "#phy-cells"
|
|
|
|
additionalProperties: false
|
|
|
|
examples:
|
|
- |
|
|
#include <dt-bindings/phy/phy.h>
|
|
combophy@d0a00000 {
|
|
compatible = "intel,combophy-lgm", "intel,combo-phy";
|
|
clocks = <&cgu0 1>;
|
|
#phy-cells = <1>;
|
|
reg = <0xd0a00000 0x40000>,
|
|
<0xd0a40000 0x1000>;
|
|
reg-names = "core", "app";
|
|
resets = <&rcu0 0x50 6>,
|
|
<&rcu0 0x50 17>,
|
|
<&rcu0 0x50 23>,
|
|
<&rcu0 0x50 24>;
|
|
reset-names = "phy", "core", "iphy0", "iphy1";
|
|
intel,syscfg = <&sysconf 0>;
|
|
intel,hsio = <&hsiol 0>;
|
|
intel,phy-mode = <PHY_TYPE_PCIE>;
|
|
intel,aggregation;
|
|
};
|