176 lines
6.0 KiB
Plaintext
176 lines
6.0 KiB
Plaintext
Binding for Silicon Labs Si5340, Si5341 Si5342, Si5344 and Si5345 programmable
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i2c clock generator.
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Reference
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[1] Si5341 Data Sheet
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https://www.silabs.com/documents/public/data-sheets/Si5341-40-D-DataSheet.pdf
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[2] Si5341 Reference Manual
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https://www.silabs.com/documents/public/reference-manuals/Si5341-40-D-RM.pdf
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[3] Si5345 Reference Manual
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https://www.silabs.com/documents/public/reference-manuals/Si5345-44-42-D-RM.pdf
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The Si5341 and Si5340 are programmable i2c clock generators with up to 10 output
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clocks. The chip contains a PLL that sources 5 (or 4) multisynth clocks, which
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in turn can be directed to any of the 10 (or 4) outputs through a divider.
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The internal structure of the clock generators can be found in [2].
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The Si5345 is similar to the Si5341 with the addition of fractional input
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dividers and automatic input selection, as described in [3].
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The Si5342 and Si5344 are smaller versions of the Si5345, with 2 or 4 outputs.
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The driver can be used in "as is" mode, reading the current settings from the
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chip at boot, in case you have a (pre-)programmed device. If the PLL is not
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configured when the driver probes, it assumes the driver must fully initialize
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it.
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The device type, speed grade and revision are determined runtime by probing.
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The driver currently does not support any fancy input configurations. They can
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still be programmed into the chip and the driver will leave them "as is".
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==I2C device node==
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Required properties:
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- compatible: shall be one of the following:
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"silabs,si5340" - Si5340 A/B/C/D
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"silabs,si5341" - Si5341 A/B/C/D
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"silabs,si5342" - Si5342 A/B/C/D
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"silabs,si5344" - Si5344 A/B/C/D
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"silabs,si5345" - Si5345 A/B/C/D
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- reg: i2c device address, usually 0x74
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- #clock-cells: from common clock binding; shall be set to 2.
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The first value is "0" for outputs, "1" for synthesizers.
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The second value is the output or synthesizer index.
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- clocks: from common clock binding; list of parent clock handles,
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corresponding to inputs. Use a fixed clock for the "xtal" input.
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At least one must be present.
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- clock-names: One of: "xtal", "in0", "in1", "in2"
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Optional properties:
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- vdd-supply: Regulator node for VDD
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- vdda-supply: Regulator node for VDDA
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- vdds-supply: Regulator node for VDDS
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- silabs,pll-m-num, silabs,pll-m-den: Numerator and denominator for PLL
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feedback divider. Must be such that the PLL output is in the valid range. For
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example, to create 14GHz from a 48MHz xtal, use m-num=14000 and m-den=48. Only
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the fraction matters, using 3500 and 12 will deliver the exact same result.
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If these are not specified, and the PLL is not yet programmed when the driver
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probes, the PLL will be set to 14GHz.
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- silabs,reprogram: When present, the driver will always assume the device must
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be initialized, and always performs the soft-reset routine. Since this will
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temporarily stop all output clocks, don't do this if the chip is generating
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the CPU clock for example.
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- silabs,xaxb-ext-clk: When present, indicates that the XA/XB pins are used
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in EXTCLK (external reference clock) rather than XTAL (crystal) mode.
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- interrupts: Interrupt for INTRb pin.
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- silabs,iovdd-33: When present, indicates that the I2C lines are using 3.3V
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rather than 1.8V thresholds.
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- vddoX-supply (where X is an output index): Regulator node for VDDO for the
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specified output. The driver selects the output VDD_SEL setting based on this
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voltage.
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- #address-cells: shall be set to 1.
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- #size-cells: shall be set to 0.
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== Child nodes: Outputs ==
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The child nodes list the output clocks.
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Each of the clock outputs can be overwritten individually by using a child node.
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If a child node for a clock output is not set, the configuration remains
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unchanged.
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Required child node properties:
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- reg: number of clock output.
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Optional child node properties:
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- silabs,format: Output format, one of:
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1 = differential (defaults to LVDS levels)
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2 = low-power (defaults to HCSL levels)
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4 = LVCMOS
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- silabs,common-mode: Manually override output common mode, see [2] for values
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- silabs,amplitude: Manually override output amplitude, see [2] for values
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- silabs,synth-master: boolean. If present, this output is allowed to change the
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multisynth frequency dynamically.
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- silabs,silabs,disable-high: boolean. If set, the clock output is driven HIGH
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when disabled, otherwise it's driven LOW.
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==Example==
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/* 48MHz reference crystal */
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ref48: ref48M {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <48000000>;
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};
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i2c-master-node {
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/* Programmable clock (for logic) */
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si5341: clock-generator@74 {
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reg = <0x74>;
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compatible = "silabs,si5341";
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#clock-cells = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&ref48>;
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clock-names = "xtal";
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silabs,pll-m-num = <14000>; /* PLL at 14.0 GHz */
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silabs,pll-m-den = <48>;
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silabs,reprogram; /* Chips are not programmed, always reset */
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out@0 {
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reg = <0>;
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silabs,format = <1>; /* LVDS 3v3 */
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silabs,common-mode = <3>;
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silabs,amplitude = <3>;
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silabs,synth-master;
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};
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/*
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* Output 6 configuration:
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* LVDS 1v8
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*/
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out@6 {
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reg = <6>;
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silabs,format = <1>; /* LVDS 1v8 */
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silabs,common-mode = <13>;
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silabs,amplitude = <3>;
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};
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/*
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* Output 8 configuration:
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* HCSL 3v3
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*/
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out@8 {
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reg = <8>;
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silabs,format = <2>;
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silabs,common-mode = <11>;
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silabs,amplitude = <3>;
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};
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};
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};
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some-video-node {
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/* Standard clock bindings */
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clock-names = "pixel";
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clocks = <&si5341 0 7>; /* Output 7 */
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/* Set output 7 to use syntesizer 3 as its parent */
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assigned-clocks = <&si5341 0 7>, <&si5341 1 3>;
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assigned-clock-parents = <&si5341 1 3>;
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/* Set output 7 to 148.5 MHz using a synth frequency of 594 MHz */
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assigned-clock-rates = <148500000>, <594000000>;
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};
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some-audio-node {
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clock-names = "i2s-clk";
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clocks = <&si5341 0 0>;
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/*
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* since output 0 is a synth-master, the synth will be automatically set
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* to an appropriate frequency when the audio driver requests another
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* frequency. We give control over synth 2 to this output here.
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*/
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assigned-clocks = <&si5341 0 0>;
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assigned-clock-parents = <&si5341 1 2>;
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};
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